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Some coreboot project code with my work
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Age
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Author
2012-05-30
Fix the location of "Setting variable MTRR" printk.
Denis 'GNUtoo' Carikli
2012-05-29
Drop config variable CPU_MODEL_INDEX
Stefan Reinauer
2012-05-08
Some more #if cleanup
Patrick Georgi
2012-05-08
Clean up #ifs
Patrick Georgi
2012-05-03
Fix register corruption during Intel Microcode update
Stefan Reinauer
2012-05-02
Don't include console.h in microcode.c when compiling with ROMCC
Stefan Reinauer
2012-05-01
Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards
Stefan Reinauer
2012-05-01
Move VSA support from x86 to Geode
Patrick Georgi
2012-05-01
Make geode_lx use the vsa from blobs repository
Patrick Georgi
2012-04-30
Fix up Sandybridge C state generation code
Stefan Reinauer
2012-04-30
Rework ACPI CST table generation
Stefan Reinauer
2012-04-27
Move top level pc80 directory to drivers/
Stefan Reinauer
2012-04-26
microcode: print date of microcode and unify output
Stefan Reinauer
2012-04-26
Revamp Intel microcode update code
Stefan Reinauer
2012-04-25
Replace cache control magic numbers with symbols
Patrick Georgi
2012-04-22
amd: Fix unused variable warning
Vikram Narayanan
2012-04-20
Revert wbind added to the reset_vector
Marc Jones
2012-04-16
S3 code in coreboot public folder.
zbao
2012-04-12
S3 code in vendorcode folder.
zbao
2012-04-11
Remove obsolete empy macro definition
Ron Minnich
2012-04-06
Fixes and Sandybridge support for lapic cpu init
Stefan Reinauer
2012-04-06
Fix support for RAM-less multi-processor init
Kyösti Mälkki
2012-04-06
Add Sandybridge/Cougar Point support to SMM relocation handler
Stefan Reinauer
2012-04-06
Cache 8MB flash instead of 4MB
Stefan Reinauer
2012-04-05
Fix timer frequency detection on Sandybridge
Stefan Reinauer
2012-04-05
Invalidate cache before first jump
Stefan Reinauer
2012-04-05
Update documentation in smmrelocate.S to mention TSEG
Stefan Reinauer
2012-04-05
Add support for Intel Sandybridge CPU
Stefan Reinauer
2012-04-04
Add support to run SMM handler in TSEG instead of ASEG
Stefan Reinauer
2012-04-03
Add support for Intel Turbo Boost feature
Stefan Reinauer
2012-04-02
Apply cache-as-ram conditionally on socket mPGA604
Kyösti Mälkki
2012-04-02
S3 code whitespaces changes.
zbao
2012-03-31
Whitespace fixes
Patrick Georgi
2012-03-31
Intel cpus: get MAXPHYADDR at runtime for new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: add hyper-threading CPU support to new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: improve CPU compatibility of new CAR
Kyösti Mälkki
2012-03-31
Add support for RAM-less multi-processor init
Kyösti Mälkki
2012-03-31
Intel cpus: apply some good programming practices in new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki
2012-03-31
Intel cpus: copy model_6ex CAR code
Kyösti Mälkki
2012-03-30
Make MTRR min hole alignment 64MB
Duncan Laurie
2012-03-30
Fix MB calculation in the reporting of the MTRR hole
Duncan Laurie
2012-03-30
MTRR: add alternate allocation method for odd memory maps
Duncan Laurie
2012-03-30
Add Kconfig options to enable TSEG and set a size
Duncan Laurie
2012-03-30
drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
Stefan Reinauer
2012-03-30
Add an option to keep the ROM cached after romstage
Stefan Reinauer
2012-03-25
Fix possible deadlock on SMP stop_this_cpu
Kyösti Mälkki
2012-03-25
Intel cpus: Fix deadlock on hyper-threading init
Kyösti Mälkki
2012-03-17
Intel cpus: Include CAR from socket
Kyösti Mälkki
2012-03-16
Rename AMD_AGESA to CPU_AMD_AGESA
Kyösti Mälkki
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