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AgeCommit message (Expand)Author
2012-02-17Remove whitespace.Patrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
2012-02-15Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki
2012-02-13AMD Geode cpus: apply un-written naming rulesKyösti Mälkki
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
2012-02-09Add Intel Socket LGA771Sven Schnelle
2012-02-09VIA cpus: apply un-written naming rulesKyösti Mälkki
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-21trivial: spelling fixes in commentsVikram Narayanan
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2012-01-09Fix Geode GX2 + LX caching for tiny bootblock.Nils Jacobs
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
2011-12-26Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones
2011-12-13Use MMCONF for all AMD family 10 CPUs.Marc Jones
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
2011-11-22k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
2011-10-13Load an IDT with NULL limitStefan Reinauer
2011-10-11Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
2011-09-07AMD F14 Rev C0 updateKerry She
2011-08-06Update AMD F14 Agesa to support Rev C0 cpusefdesign98
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-22Add SSE3 dependent codeefdesign98
2011-07-22Update AMD SR5650 and SB700efdesign98
2011-07-18Add AMD Family 10 support to cpu folderefdesign98
2011-07-13Make AMD SMM SMP awareRudolf Marek
2011-07-04Small SMM fixupsRudolf Marek
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
2011-05-15Cosmetic cleanup.Scott Duplichan
2011-05-15Correct the number of MCA error reporting banks cleared.Scott Duplichan
2011-05-151) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.Scott Duplichan
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