summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2017-06-28cpu/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2017-06-28cpu/intel/pineview: Include speedstepArthur Heymans
2017-06-28cpu/*: Add whitespace around '<<'Elyes HAOUAS
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
2017-06-27cpu/x86/smm: allow SSE instructions in SMM modulesAaron Durbin
2017-06-22cpu/allwinner/a10/clock.h: Add missing bracketElyes HAOUAS
2017-06-22cpu/x86: Use do while loopPaul Menzel
2017-06-22cpu/x86/sipi_vector: use macros for CR0 flagsAaron Durbin
2017-06-22cpu/x86/smm: use macros for CR0 flagsAaron Durbin
2017-06-22cpu/x86/smm: fix up types in module loaderAaron Durbin
2017-06-19cpu/x86/smm/smihandler: Apply cosmetic changesPatrick Rudolph
2017-06-16cpu/x86/mp_init: report correct count of AP acceptanceAaron Durbin
2017-06-16haswell: add CBMEM_MEMINFO table when initing RAMMatt DeVillier
2017-06-13cpu/x86/mtrr: fail early if solution exceeds available MTRRsAaron Durbin
2017-06-13cpu/amd/fam10/ram_calc: Remove superfluous guardArthur Heymans
2017-06-12src/cpu/amd/model_fxx/powernow_api.c Fix checkpatch errors + warningsEvelyn Huang
2017-06-12src/cpu/amd/atrr/amd_mtrr.c Fix checkpatch errors + warningsEvelyn Huang
2017-06-12src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errorsEvelyn Huang
2017-06-12cpu/x86: fix spelling mistakeMartin Roth
2017-06-09cpu/amd/car: Fix checkpatch warningsEvelyn Huang
2017-06-09cpu/intel/model_206ax: Use tsc monotonic timerPatrick Rudolph
2017-06-07src: change coreboot to lowercaseMartin Roth
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
2017-05-30arch/x86: Add function to determine if we're currently running from CARJulius Werner
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
2017-05-18AMD MTRR: Add common add_uma_resource_below_tolm()Kyösti Mälkki
2017-05-16cpu/intel/turbo: Add option to disable turboSubrata Banik
2017-04-28nb/amd/amdk8: Link reset_test.cArthur Heymans
2017-04-27nb/amd/amdk8: Link raminit_f.cArthur Heymans
2017-04-15AGESA: Unify heap locationKyösti Mälkki
2017-04-08arch/x86: remove CAR global migration when postcar stage is usedAaron Durbin
2017-04-06northbridge/amd/stoney: Add FT4 packageMarshall Dawson
2017-04-05AGESA: Disable CAR with empty stackKyösti Mälkki
2017-04-05AGESA: BIST is already preservedKyösti Mälkki
2017-04-05AGESA: Move romstage main entry under cpuKyösti Mälkki
2017-04-05AGESA: Move amd_initmmio() callKyösti Mälkki
2017-04-04AGESA: Reduce typecasting in heapmanager callsKyösti Mälkki
2017-04-04AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanlyKyösti Mälkki
2017-04-04AGESA: Adjust heap location for S3 resume pathKyösti Mälkki
2017-04-04AGESA: Refactor S3 support functionsKyösti Mälkki
2017-03-28AGESA: Fork for new cache-as-ram init codeKyösti Mälkki
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
2017-03-19cpu/x86: add a barrier with timeoutBora Guvendik
2017-03-16binaryPI: Fix SSE regression and align stack earlyKyösti Mälkki
2017-03-16cpu/intel: Fix the remaining issues detected by checkpatchLee Leahy
2017-03-16cpu/intel: Wrap lines at 80 columnsLee Leahy
2017-03-16cpu/intel: Fix brace issues detected by checkpatch.plLee Leahy
2017-03-16cpu/intel: Add int to unsignedLee Leahy
2017-03-16cpu/intel: Fix the spacing issuesLee Leahy
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 14:43:19 +0000