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path: root/src/cpu
AgeCommit message (Expand)Author
2012-11-07Leave power control registers unlockedSameer Nanda
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
2012-11-05Overhaul speedstep codeNico Huber
2012-11-05Fix some indentation flaws and break very long linesNico Huber
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
2012-11-02Correct FSB reading in speedstep ACPINico Huber
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-10-30Add support for socket LGA775Stefan Tauner
2012-10-07Fix typo in mPGA603 socketKyösti Mälkki
2012-10-07Remove chip.h files without config structureKyösti Mälkki
2012-09-19C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C3...Siyuan Wang
2012-09-05VIA Nano: Add support for VIA Nano CPUsAlexandru Gagniuc
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
2012-08-27Intel model_106cx: change CAR to HT-capableKyösti Mälkki
2012-08-22Auto-declare chip_operationsKyösti Mälkki
2012-08-09Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
2012-08-04Make the device tree available in the rom stageStefan Reinauer
2012-08-03Intel CPUs: Fix counting of CPU coresKyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
2012-07-25Fix date output in Microcode updateStefan Reinauer
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add microcode blob processingVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Make MAX_PHYSICAL_CPUS invisible on non-AMD boardsStefan Reinauer
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
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