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path: root/src/cpu
AgeCommit message (Expand)Author
2006-05-06Use a real variable to configure rom base for vsa ...Ronald G. Minnich
2006-05-04fix the treeStefan Reinauer
2006-05-04core range and set_init_ram_accessYinghai Lu
2006-05-04rm unused fileYinghai Lu
2006-05-04merge zrom to rom_stream and print olen ilenYinghai Lu
2006-05-03oops! Slap me on the head for this one. Quick fix for ward untilStefan Reinauer
2006-05-02add automatic payload compression method to LinuxBIOSStefan Reinauer
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
2006-04-27code cleanup, comments addedLi-Ta Lo
2006-04-20boot to kernelLi-Ta Lo
2006-04-13add SystemPreInit() and supportRonald G. Minnich
2006-04-13minor modificationLi-Ta Lo
2006-04-10add cpureginit to romcc code.Ronald G. Minnich
2006-04-10clean up gx2def.h a bit. Ronald G. Minnich
2006-04-06add bug support for 2.1Ronald G. Minnich
2006-04-06reformat Li-Ta Lo
2006-04-06more fix for vsm, not working yetLi-Ta Lo
2006-04-03did I commit the last change?Li-Ta Lo
2006-04-03new cache_as_ram support Yinghai Lu
2006-03-22added this fileRonald G. Minnich
2006-03-21add vsm supportRonald G. Minnich
2006-03-21cpubug is fine. Ronald G. Minnich
2006-03-20added definitions. added cpubug support. added object. Commented out Ronald G. Minnich
2006-03-19small cleanup attempt in sc520 code. there needs to be some major springStefan Reinauer
2006-03-17- sc520 updates. move PAR setup to mainboard auto.cStefan Reinauer
2006-03-17fix mmcrval, small cosmetics to raminitStefan Reinauer
2006-02-28remove unused GX1 asm codeLi-Ta Lo
2006-02-27more GX2 commitLi-Ta Lo
2006-01-28renameRonald G. Minnich
2006-01-27adding preliminary, and almost certainly wrong, rumba support. Ronald G. Minnich
2006-01-09don't need copy_secondary_start_to_1m_below for non-smpYinghai Lu
2006-01-041M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above supportYinghai Lu
2005-12-14indirect jmp with *Yinghai Lu
2005-12-14from issue 53: don't set TOM2 if 4G less mem installed, opt for init_eccYinghai Lu
2005-12-14support HDT disassembly when cache as ram auto stageYinghai Lu
2005-12-14issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1MYinghai Lu
2005-12-09make clear_1m_ram.c to support gcc 3 and gcc4Yinghai Lu
2005-12-07use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50Yinghai Lu
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
2005-12-01Applying YhLu's patch from issue 37.Stefan Reinauer
2005-12-01Applying 11_26_car_tyan.diff from Yinghai Lu.Stefan Reinauer
2005-11-26- Apply 11_24_a_s1_core.diff fromStefan Reinauer
2005-11-26add another Via C3 cpu id reported by grzegorz@el-kom.plStefan Reinauer
2005-11-23remove rev f ifdefRonald G. Minnich
2005-11-23CAR patch from YH LURonald G. Minnich
2005-11-23Split out microcode updates.Ronald G. Minnich
2005-11-23missed these.Ronald G. Minnich
2005-11-23issue 25, various AMD patchesRonald G. Minnich
2005-11-22fixed fsf addressRonald G. Minnich
2005-11-22EPIA-M fixupRonald G. Minnich
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