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2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-16x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRsMarshall Dawson
AMD's fixed MTRRs have RdDram and WrDram bits that route memory accesses to DRAM vs. MMIO. These are typically hidden for normal operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at reset, should be set for configuration during POST, then cleared for normal operation. Attempting to modify the RdDram and WrDram settings without unhiding them causes a General Protection Fault. Add functions to enable and disable MtrrFixDramModEn. Unhide/hide as necessary when copying or writing the fixed MTRRs. Finally, modify sipi_vector.S to enable the bits prior to writing the fixed MTRRs and disable when complete. This functionality is compiled out on non-AMD platforms. BUG=b:68019051 TEST=Boot Kahlee, check steps with HDT Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15cpu/x86/16bit/entry16.inc: Fix typo in commentPaul Menzel
Add the missing *r* of the possessive pronoun *your*. Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/23758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-02-06cpu/intel/haswell: Don't select PARALLEL_CPU_INITArthur Heymans
PARALLEL_CPU_INIT pertains to initialize_cpus() in src/cpu/x86/lapic/lapic_cpu_init.c which haswell does not use as it uses PARALLEL_MP init. Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25cpu/x86: don't utilize UDELAY_IO if GENERIC_UDELAYAaron Durbin
If GENERIC_UDELAY is selected don't try to use UDELAY_IO as there will be a udelay() conflict at link time. BUG=b:72378235,b:72170796 Change-Id: I9e01c9daddd0629ecc38a809889b39a505c0e203 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24AGESA f15 cimx/sb700: Remove unused chips codeKyösti Mälkki
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18cpu/intel: Remove unused CPU codeArthur Heymans
Change-Id: I44574e64e621ea60d559d593694af36c648fb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17AGESA f15 boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i5000 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i5000 Mainboards: mainboard/supermicro/x7db8 mainboard/asus/dsbf Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel sch board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/intel/sch Mainboards: mainboard/iwave/iWRainbowG6 Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/dmp/vortex86ex Mainboards: mainboard/dmp/vortex86ex Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15AMD GX2 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-20cpu/x86: set permanent SMM handler stack to 1KiBAaron Durbin
Not all SMM save state sizes equate to having enough stack in the permanent SMM handler. Therefore, ensure 1KiB of stack is available for each cpu's stack. Intel's save state size is 1KiB, but AMD's save state size is only 512. Therefore, decouple save state size from the per cpu stack size. BUG=b:70027919 Change-Id: I54b9e6f3cc0ad6ca3d7b60b2b422b5dc5a78a552 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-11intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2cElyes HAOUAS
Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-30intel: Replace msr(0x198) with msr(IA32_PERF_STATUS)Elyes HAOUAS
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07Microcode: add dependency to header filesJulien Viard de Galbert
When using microcode header and updating the header (due to a new release of microcode during early development) the build system doesn't detect the header change. This commit fixes this by adding the appropriate dependency. Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/22307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07cpu/intel: Add Intel FCBGA1023 socket supportHal Martin
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013. select SSE2 per review suggestion Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-04cpu/intel/speedstep: Emit PPKG object for first packageNico Huber
Tested on Lenovo Thinkpad T500. Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04cpu: assume SSE if SSE2 is selectedAaron Durbin
If the SSE2 Kconfig option is selected also select SSE. Change-Id: I6ccba57d5ae13b8066f2f744cd739282ffd4fe73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-10-31AMD boards: Fix function name (soft_reset) in messageJonathan Neuschäfer
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-10-31x86/lapic: Use the existing lapicid() functionMarc Jones
coreboot has a lapicid() function, so use it. Change-Id: I7f536c229f271674c34d722b5db96ce665b720f1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-29cpu/intel/model_1067x: Select UDELAY_LAPICArthur Heymans
This was moved out of northbridge/gm45 but was accidentally? commented out in c5d972d073c "Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig" The intel eagleheights mainboard also uses UDELAY_LAPIC with this change and is untested. Change-Id: I70e51fa50935baf187cef60f2e636251b40d6475 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22172 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-16cpu/amd: Fix spelling of *implementation*Paul Menzel
Change-Id: I3ef810ee59492c8d7147934e61523c8fd223863b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16cpu/x86/mtrr: Remove var-MTRR alignment optimizationNico Huber
The code used to split up ranges >64MiB into 64MiB-aligned and unaligned parts. However in its current state the next step, calc_var_mtrr_range(), results in the same allocation, no mat- ter if we split the range up before. So just drop the split-up. Change-Id: I5481fbf3168cdf789879064077b63bbfcaf122c9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-05AGESA vendorcode: Add ENABLE_MRC_CACHE optionKyösti Mälkki
When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02binaryPI: Fix boot regressionsKyösti Mälkki
Fix boot regression after commit d4955f0 AGESA: Move API interface under drivers/ Boards were left without cache-as-ram setup code and appeared completely dead. Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-10-02cpu/x86: Align stack in SIPI handlerMarshall Dawson
Ensure the stack is properly aligned in the SIPI handler. This avoids an exception when an aligned instruction is performed on stack data. BUG=b:66003093 TEST=boot kahlee built with gcc 6.3 Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-29AGESA binaryPI: Fix indirect AGESA.h includeKyösti Mälkki
Change-Id: I5e2affe337f7e61ca79530b3a77af963e8692ff1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
Except for family15, all AGESA boards have moved away from AGESA_LEGACY_WRAPPER, thus they all have POSTCAR_STAGE now. AGESA family15 boards remain at AGESA_LEGACY=y, but those boards have per-board romstage.c files and are not touched here. Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17cpu/x86/sipi_vector.S: Use correct op suffixDamien Zammit
clang wont compile `cmp` asm opcode because it's ambiguous, use the correct op suffix `cmpl` Change-Id: I82da5a9065b382e182dc7d502c7dca2fc717543b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Drop heapManager.h includesKyösti Mälkki
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12cpu/intel/slot_1: Increase CAR size to 8KiBKeith Hui
Because cpu/intel/car/romstage.c assumes a 8KiB stack size when setting up stack guards, and all Slot 1 compatible CPUs have enough L1 cache available for the increase. Adjust DCACHE_RAM_BASE to match. Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz Tualeron. The latter actually requires this patch to boot successfully. Change-Id: I5b440e7be4f3149378db88872872012c92049c20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-12cpu/intel/car/cache_as_ram.inc: Fix long standing issuesKeith Hui
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. Do not set %ebp before and switch directly to stack returned by romstage_main(). Remove an unneeded 4-byte gap in CAR stack. The caching strategy for flash XIP area should be WRPROT. Clarify the various comments in the file on the logic. Together they lay the groundwork for bringing EARLY_CBMEM_INIT to intel/slot_1 boards. Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21503 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove unused codeKeith Hui
Remove CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21502 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12cpu/intel/car/cache_as_ram.inc: Remove broken HT codeKeith Hui
Remove Hyperthreading related code that was missing setup of SIPI vector and did not work. Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21375 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin
The original purpose of adjust_cpu_apic_entry() was to set up an APIC map. That map was effectively only used for mapping *default* APIC id to CPU number in the SMM handler. The normal AP startup path didn't need this mapping because it was whoever won the race got the next cpu number. Instead of statically calculating (and wrong) just initialize the default APIC id map when the APs come online. Once the APs are online the SMM handler is loaded and the mapping is utilized. Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-10AGESA binaryPI: Remove heapmanager from romstageKyösti Mälkki
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved from romstage to ramstage, heapamanager in romstage is no longer needed. Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-09ACPI S3: Handle LATE_CBMEM_INIT boardsKyösti Mälkki
Followup removes inlined acpi_is_wakeup_s3() from PRE_RAM, and new implementation depends of CAR_GLOBAL. Change-Id: Iea1c5ab2175f8d496baa09bd6137cacc912df2cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 04:44:15 +0000