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AgeCommit message (Expand)Author
2014-07-17misc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-14AGESA fam15: Fix entry to cimx/sb900Kyösti Mälkki
2014-07-14AGESA CIMx: Move late init out of get_bus_conf()Kyösti Mälkki
2014-07-14AGESA: Trace execution with AGESAWRAPPER()Kyösti Mälkki
2014-07-14AMD SPI: Optimise for longer writesKyösti Mälkki
2014-07-11src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
2014-07-03AGESA: Call get_bus_conf() just onceKyösti Mälkki
2014-07-03AGESA: Add agesawrapper_post_device()Kyösti Mälkki
2014-07-03AGESA boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
2014-07-03AGESA: Clean separation of SPI flashKyösti Mälkki
2014-07-03AGESA boards: Add prepare_for_resume()Kyösti Mälkki
2014-07-03AGESA S3: Refactor S3 backup store locations in SPIKyösti Mälkki
2014-06-30x86 MTRR: Drop unused return valueKyösti Mälkki
2014-06-30Use MTRR definesKyösti Mälkki
2014-06-29cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always falseEdward O'Callaghan
2014-06-29cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII artEdward O'Callaghan
2014-06-28Don't add .eh_frame sections to SMM imagePatrick Georgi
2014-06-25AGESA: Move config parameters for non-volatile S3 dataKyösti Mälkki
2014-06-25Declare acpi_is_wakeup_early() only onceKyösti Mälkki
2014-06-21cpu/amd/agesa: Use acpi_is_wakeup()Kyösti Mälkki
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
2014-06-06AGESA: Use common heap allocatorKyösti Mälkki
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
2014-05-19build: use CFLAGS_* in more places where they're neededPatrick Georgi
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
2014-05-13cpu/intel: Add CPU socket rPGA988BZaolin
2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
2014-05-09Intel FSP: add a shared set of functions for the FSPMartin Roth
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
2014-05-05haswell: move to mp_init libraryAaron Durbin
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
2014-04-30console: Move UART port defaults to mainboardKyösti Mälkki
2014-04-30console: Drop EARLY_CONSOLE optionKyösti Mälkki
2014-04-30allwinner/a10: Hide SoC specific UART functionsKyösti Mälkki
2014-04-30uart: Support multiple portsKyösti Mälkki
2014-04-29AGESA SPI: Fix Kconfig optionsKyösti Mälkki
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
2014-04-20Move MAX_PHYSICAL_CPUS to AMD k8 and fam10Kyösti Mälkki
2014-04-18console: Use romstage code for ramstage and SMMKyösti Mälkki
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