Age | Commit message (Expand) | Author |
2012-01-23 | post code: Replaced hard-coded post code with macro | Vikram Narayanan |
2012-01-21 | trivial: spelling fixes in comments | Vikram Narayanan |
2012-01-20 | Leave SSE and MMX instructions enabled in coreboot | Stefan Reinauer |
2012-01-10 | MTRR: get physical address size from CPUID | Sven Schnelle |
2012-01-09 | Fix Geode GX2 + LX caching for tiny bootblock. | Nils Jacobs |
2012-01-09 | ACPI: mark empty get_cst_entries() weak | Sven Schnelle |
2011-12-26 | Fix Fam10 MMCONF_SUPPORT_DEFAULT setting. | Marc Jones |
2011-12-13 | Use MMCONF for all AMD family 10 CPUs. | Marc Jones |
2011-12-05 | Bootblock does not need a unique boot_cpu() | Kyösti Mälkki |
2011-11-24 | Remove unused code files and cosmetic changes | Kyösti Mälkki |
2011-11-22 | k8 raminit: add workaround for erratum #181 on non-fam-f | Florian Zumbiehl |
2011-11-22 | Fix post_code in 16bit entry | Kyösti Mälkki |
2011-11-01 | remove trailing whitespace | Stefan Reinauer |
2011-11-01 | Remove XIP_ROM_BASE | Patrick Georgi |
2011-10-30 | Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9 | Rudolf Marek |
2011-10-28 | Get rid of the old romstage-as-bootblock ROM layout | Patrick Georgi |
2011-10-28 | Get rid of AUTO_XIP_ROM_BASE | Patrick Georgi |
2011-10-25 | SPEEDSTEP: write _CST tables | Sven Schnelle |
2011-10-18 | Activate older Xeon P4 microcodes | Kyösti Mälkki |
2011-10-17 | Fixes several issues with amd k8 SSDT P-state generation | Oskar Enoksson |
2011-10-15 | SMM: Move wbinvd after pmode jump | Stefan Reinauer |
2011-10-13 | Load an IDT with NULL limit | Stefan Reinauer |
2011-10-11 | Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E | Oskar Enoksson |
2011-09-24 | Add AMD Family 10h PH-E0 support | QingPei Wang |
2011-09-12 | Miscellaneous AMD F14 warning fixes | efdesign98 |
2011-09-09 | Crank up CPU speed on Intel Core and Core2 CPUs | Patrick Georgi |
2011-09-07 | AMD F14 Rev C0 update | Kerry She |
2011-08-06 | Update AMD F14 Agesa to support Rev C0 cpus | efdesign98 |
2011-08-04 | cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. | Keith Hui |
2011-07-22 | Add SSE3 dependent code | efdesign98 |
2011-07-22 | Update AMD SR5650 and SB700 | efdesign98 |
2011-07-18 | Add AMD Family 10 support to cpu folder | efdesign98 |
2011-07-13 | Make AMD SMM SMP aware | Rudolf Marek |
2011-07-04 | Small SMM fixups | Rudolf Marek |
2011-06-28 | Addition of Family12/SB900 wrapper code | efdesign98 |
2011-06-22 | Move existing AMD Ffamily14 code to f14 folder | efdesign98 |
2011-06-22 | Rename {CPU|NB|SB}/amd/*_wrapper folders | efdesign98 |
2011-06-18 | SMM: flush caches after disabling caching | Sven Schnelle |
2011-06-15 | SMM: don't overwrite SMM memory on resume | Sven Schnelle |
2011-05-15 | Cosmetic cleanup. | Scott Duplichan |
2011-05-15 | Correct the number of MCA error reporting banks cleared. | Scott Duplichan |
2011-05-15 | 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization. | Scott Duplichan |
2011-05-10 | Change read_option() to a macro that wraps some API uglyness | Patrick Georgi |
2011-05-10 | This replaces the fixed shift values in the apic timer init with macros. | Vikram Narayanan |
2011-05-03 | Enable caching for ROM area in model_6ex/cache_as_ram.inc | Sven Schnelle |
2011-04-26 | Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an | Stefan Reinauer |
2011-04-21 | more ifdef -> if fixes. | Stefan Reinauer |
2011-04-21 | more ifdef -> if fixes | Stefan Reinauer |
2011-04-19 | Fix some more misuses of ifdef/if defined | Stefan Reinauer |
2011-04-14 | drop half an uart8250 implementation from smiutil and use the common code | Stefan Reinauer |