summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Expand)Author
2012-08-09Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
2012-08-04Make the device tree available in the rom stageStefan Reinauer
2012-08-03Intel CPUs: Fix counting of CPU coresKyösti Mälkki
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
2012-07-25Fix date output in Microcode updateStefan Reinauer
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
2012-07-24Add microcode blob processingVadim Bendebury
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
2012-07-24Make MAX_PHYSICAL_CPUS invisible on non-AMD boardsStefan Reinauer
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
2012-07-22AMD CPUs: Updated CPU list in powernow_acpi.cJukka Rantala
2012-07-18AMD northbridges: drop dead codeKyösti Mälkki
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
2012-07-16AMD MTRR: fix rounding and renamesKyösti Mälkki
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-14Remove useless file from building.zbao
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 08:00:23 +0000