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2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/555 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-15Intel model_106cx: Use symbolic names for MTRR bitsKyösti Mälkki
Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/637 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-13AMD Geode cpus: apply un-written naming rulesKyösti Mälkki
Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Rename directories and Kconfig as follows: model_lx -> geode_lx model_gx1 -> geode_gx1 model_gx2 -> geode_gx2 Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/618 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-09Add Intel Socket LGA771Sven Schnelle
Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/492 Tested-by: build bot (Jenkins)
2012-02-09VIA cpus: apply un-written naming rulesKyösti Mälkki
Rename files and directories: model_c3 -> c3 model_c7 -> c7 Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/614 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
Added a macro in the post code list, which replaces hard coded value in cpu/x86/cache/cache.c Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-21trivial: spelling fixes in commentsVikram Narayanan
Few spelling fixes in entry16.inc Change-Id: Iad3d18eee3f498171cb766589aaebefdcf0e9767 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX instructions in the CPU after romstage. Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/553 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
The current code uses static values for the physical address size supported by a CPU. This isn't always the right value: I.e. on model_6[ef]x Core (2) Duo CPUs physical address size is 36, while Xeons from the same family have 38 bits, which results in invalid MTRR setup. Fix this by getting the right number from CPUID. Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-09Fix Geode GX2 + LX caching for tiny bootblock.Nils Jacobs
Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/528 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
This function prevents the linker from choosing the right get_cst_entries(), preventing writing the _CST tables. Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821 Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/496 Tested-by: build bot (Jenkins)
2011-12-26Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones
I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location. Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/487 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-13Use MMCONF for all AMD family 10 CPUs.Marc Jones
This fixes problems in AP init when multiple APs are trying to access PCI config space. All Fam10 CPUs setup and support MMCONF. Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/455 Tested-by: build bot (Jenkins) Reviewed-by: Alec Ari <neotheuser@ymail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-22k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl
Disable DRAM controller on non-fam-f CPUs not using fam-f register layout. Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/448 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
Relocate early post_code() so it gets executed and does not corrupt BIST at %eax. Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
It is meant to be a address and not a dereference. Otherwise MTRR is filled with code and not with the address. This is what I hate at most on the AT&T syntax. Instead of taking the address, it was a dereference. Not greatly visible, except I wondered why opcode is not 0xb4 but 0xa1 and it took another half an our to see it. Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/358 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
Change-Id: Idb4b57044808918de343d31519768d0986840f01 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
As new microcode files were included, the table was not updated with families 0f25 and 0f26. Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
First issue fixed: For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug by really emitting one Processor object for each core. However, the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Fourth issue: If a processor without PowerNow! support was inserted in a system with coreboot configured with SET_FIDVID then the boot process hanged mysteriously and very early. Apparently because init_fidvid_ap tampers with non-existing registers. This commit fixes the bug by bailing out from init_fidvid_ap if PowerNow! capability is missing. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 Reviewed-on: http://review.coreboot.org/239 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
According to Rudolf Marek putting a memory instruction between the CR0 write and the jmp in protected mode switching might hang the machine. Move it after the jmp. There might be a better solution for this, such as enabling the cache, as keeping it disabled does not prevent cache poisoning attacks, so there is no real point. However, Intel docs say that SMM code in ASEG is always running uncached, so we might want to consider running SMM out of TSEG instead, as well. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec Reviewed-on: http://review.coreboot.org/283 Reviewed-by: Sven Schnelle <svens@stackframe.org> Tested-by: build bot (Jenkins)
2011-10-13Load an IDT with NULL limitStefan Reinauer
Load an IDT with NULL limit to prevent the 16bit IDT being used in protected mode before c_start.S sets up a 32bit IDT when entering ram stage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e Reviewed-on: http://review.coreboot.org/259 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson
AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to mark dram memory above 4GB as WB. However, AMD K8 rev E and earlier don't implement this bit and therefore need MTRR spanning dram memory above 4GB. The current implementation of amd_setup_mtrrs never generate MTRR above 4GB. This caused memory > 4GB not to be recognized in e.g. Linux on those rev E or older platforms. This commit should fix that bug. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1 Reviewed-on: http://review.coreboot.org/238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/202 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
This commit adds in some more fixes to AMD F14 compile warnings. The change in the mtrr.c file is in prep- aration for changes yet to com, but it is currently innocuous. Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/133 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
The CPUs start on their slowest speed, and were left that way by coreboot. This change will speed up coreboot a bit, as well as systems that don't change the clock for whatever reason. Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/176 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 Rev C0 updateKerry She
Add AMD Family14 Rev C0 cpu id Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/160 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-06Update AMD F14 Agesa to support Rev C0 cpusefdesign98
This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-22Add SSE3 dependent codeefdesign98
This change separates out changes that were initially found in the commit for XHCI and AHCI changes to "arch/x86/Makefile. inc". It also corrects a comment. The SSE3 dependent code adds a pair of CR4 access functions and a blob of code that re-sets CR4.OSFXSR and CR4.OSXMMEXCPT. Change-Id: Id97256978da81589d97dcae97981a049101b5258 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-18Add AMD Family 10 support to cpu folderefdesign98
This change adds the AMD Family 10 cpu support to the cpu folder. It also updates the makefiles of the Families 12 and 14 to take advantage of a pair of shared files that are moved to the cpu/agesa folder. Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/97 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-13Make AMD SMM SMP awareRudolf Marek
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define, later all 0xa0000 could be changed to use it. Remove the unnecessary test if the smm_init routine is called once (it is called by BSP only) and also remove if lock bit is set becuase this bit is cleared by INIT it seems. Add the defines for fam10h and famfh to respective files, we do not have any shared AMD MSR header file. Tested on M2V-MX SE with dualcore CPU. Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/82 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-04Small SMM fixupsRudolf Marek
Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG). While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just spinlocking. The rep nop could not be used because "as" complains that rep is used without string instructions. Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/81 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction. For reference, the mail i've sent to ML with the bugreport: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking/undocking works: 1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock) 2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows: a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range b) Store(0, 0x808) // Generates I/O Trap to SMM c) // SMM is executed d) Return (SMIF) // Return Result in SMIF I've verified that a) is really executed with ACPI debugging in the Linux Kernel. It writes the correct value to GNVS Memory. After that, i've logged the SMIF value in SMM, which contains some random (or former) value of SMIF. So i've added the GNVS area to /proc/mtrr which made things work. I've also tried a wbinvd() in SMM code, with the same result. After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized that it starts with: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ data32 ljmp $0x08, $1f ...which disables caching in SMM code, but doesn't flush the cache. So the problem is: - the linux axpi write to the SMIF GNVS Area will be written to Cache, because GNVS is WB - the SMM code runs with cache disabled, and fetches SMIF directly from Memory, which is some other value Possible Solutions: - enable cache in SMM (yeah, cache poisoning...) - flush caches in SMM (really expensive) - mark GNVS as UC in Memory Map (will only work if OS really marks that Area as UC. Checked various vendor BIOSes, none of them are marking NVS as UC. So this seems rather uncommon.) - flush only the cache line which contains GNVS. Would fix this particular problem, but users/developers could see other Bugs like this. And not everyone likes to debug such problems. So i won't like this solution. Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/39 Tested-by: build bot (Jenkins)
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-05-15Cosmetic cleanup.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Correct the number of MCA error reporting banks cleared.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-151) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.Scott Duplichan
2) Remove coreboot variable MTRR initialization because AMD reference code handles it. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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