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2012-04-30Rework ACPI CST table generationStefan Reinauer
... in order to unify the Sandybridge and Lenovo implementations currently used in the tree. - use acpi_addr_t in acpigen_write_register() - use acpi_cstate_t for cstate tables (and fix up the x60 and t60) - drop cst_entry from acpigen.h Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/943 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/939 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
Most subsystems print their name with a colon, and then the message. Do the same thing for the microcode update code. Also, each microcode update has a date header. Print the date from that header to make it easier to determine whether you're running the latest microcode. Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/929 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-26Revamp Intel microcode update codeStefan Reinauer
- add GPLv2 + copyright header after talking to Ron - "bits" in struct microcode served no real purpose but getting its address taken. Hence drop it - use asm volatile instead of __asm__ volatile - drop superfluous wrmsr (that seems to be harmless but is still wrong) in read_microcode_rev - use u32 instead of unsigned int where appropriate - make code usable both in bootblock and in ramstage - drop ROMCC style print_debug statements - drop microcode update copy in Sandybridge bootblock Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
Instead of opaque numbers like (1<<29), use symbols like CR0_NoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-22amd: Fix unused variable warningVikram Narayanan
Comment out the id variable which is used in a commented code block. Change-Id: Ib002d57e5314971f0589d04b7e451ab7d7079f53 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/913 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-20Revert wbind added to the reset_vectorMarc Jones
This change reverts : Change Id I4fdb281b2b684ab5fea999aae28ca08dce24da4d The wbinvd (or invd) should not be needed at the reset vector. It causes problems with some CPUs AP init. If there is a problem with a specific CPU and it must be done at this location, it should be added conditionally. Change-Id: I85b71b0a07f039359a4fb889aaa05c75fff619be Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/908 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-16S3 code in coreboot public folder.zbao
1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-12S3 code in vendorcode folder.zbao
Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-11Remove obsolete empy macro definitionRon Minnich
In the early days of v2 the (e.g.) #ifdef SMP style was frowned upon in some quarters. Hence, empty definitions of functions were created. This particular function, possibly the last remaining example, was no longer even being used anywhere. Signed-off-by: Ron Minnich <rminnich@gmail.com>
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
- preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/871 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300 Only align 16-bit entry on platforms that really require it, indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of AP_SIPI_VECTOR for platforms not depending on this feature. Build of romstage should be fixed to get the vector address from bootblock build automatically. Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
Previously this part of smmrelocate.S had to be omitted because the CONFIG_ options for those components did not exist yet. Add them back. Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/874 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/873 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/870 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Invalidate cache before first jumpStefan Reinauer
Some CPUs (Sandybridge) seem to require this, and it does not hurt on other CPUs. Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/869 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/861 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie@google.com> Acked-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
From wikipedia: Intel Turbo Boost is a technology implemented by Intel in certain versions of their Nehalem- and Sandy Bridge-based CPUs, including Core i5 and Core i7 that enables the processor to run above its base operating frequency via dynamic control of the CPU's "clock rate". It is activated when the operating system requests the highest performance state of the processor. Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/844 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/607 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02S3 code whitespaces changes.zbao
some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-31Whitespace fixesPatrick Georgi
Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/834 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
Use CPUID to get MAXPHYADDR and set MTRR masks correctly. Also only BSP CPU clears MTRRs and initializes its Local APIC. Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/686 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/604 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/644 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/454 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
Delete dead CAR code and whitespace fixes. Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/643 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/641 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/606 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
With >= 4GB memory installed we get a memory map split in the middle due to remap that has boundaries that are inconveniently aligned for MTRRs due to the various UMA regions. 0000MB-2780MB 2780MB RAM (writeback) 2780MB-2782MB 2MB TSEG (uncached/SMRR) 2782MB-2784MB 2MB GFX GTT (uncached) 2784MB-2816MB 32MB GFX UMA (uncached) 2816MB-4096MB 1280MB EMPTY (N/A) 4096MB-5368MB 1272MB RAM (writeback) 5368MB-5376MB 8MB ME UMA (uncached) The default MTRR allocation method of trying to cover everything with one MTRR and then carve out a single uncached region does not work for the GPU aperture which needs write-combining type, and it also has issues trying to cover the uneven boundaries in the avaiable variable MTRRs. My goal was to make a minimal set of changes and avoid modifying behavior on existing systems with an algorithm that is not always optimal for a typical memory layout. So the flag 'above4gb=2' will change these allocation behaviors: 1) Detect the number of available variable MTRRs rather than limiting to hardcoded value. We need every last MTRR. 2) Don't try to cover all RAM with one MTRR, instead let each RAM region get covered independently. 3) Don't assume uma_memory_base is part of the last region and increase the size of that region. In this case the UMA region is carved out from the lower memory region and it is already declared as part of the ram region. 4) If a memory region can't be covered with MTRRs >= 16MB then instead make a larger region and trim it with uncached MTRRs. Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add Kconfig options to enable TSEG and set a sizeDuncan Laurie
Future CPUs will require TSEG use for SMM Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
Do not use printk on the running thread after it has been sent the INIT IPI, execution may halt with console spinlock held. Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/776 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
Only the BSP CPU was able to start its hyper-threading CPU siblings. When an AP CPU attempts this it calls start_cpu() within start_cpu(), deadlocking the system with start_cpu_lock. At the time intel_sibling_init() is run, the BSP CPU is still walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus(). A sibling CPU appended at the end of this list will get started. Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode updates on hyper-threading sibling CPUs must be serialized. Tested with HT-enabled P4 Xeons on dual-socket604 platform. Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/775 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
It was not obvious which CAR was compiled in. Also build would fail if a socket included two models with both having an include for CAR. Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Break the circular dependency with family15 Kconfig. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
So set their XIP configuration to ROM_SIZE. Change-Id: I6c1abccec3b1d7389c85df55343ff0fc68a61eec Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/797 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins)
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
In a case of CS & 0x0fff != 0x0, lidt memory operand does not point to nullidt, this can raise an exception and shutdown the CPU. When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts execute at physical address 000yz000H. Seems this translates to either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model. With the change entry16.inc is relocatable as the commentary suggests and can be used as ap_sipi_vector on SMP systems. Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/707 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-09move console includes to central console/console.hStefan Reinauer
Because it's included everywhere anyways. Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/691 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-20Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.Marc Jones
The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/627 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Remove whitespace.Patrick Georgi
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh
Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/555 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16Intel cpus: use CPU_PHYSMASK_HI define in CARKyösti Mälkki
Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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