summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Collapse)Author
2009-09-15Don't mix int and boolean for kconfig variables. It might work, it might not.Patrick Georgi
trivial change. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-04Use driver-y instead of obj-y for model_6xx_init.o.Uwe Hermann
Otherwise booting (but not building) fails: Initializing CPU #0 CPU: vendor Intel device 665 CPU: family 06, model 06, stepping 05 Unknown cpu This patch was tested to fix the issue on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29File I missed committing.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29This is the final set of changes to allow rumba to build. Rumba is notRonald G. Minnich
tested. I also addressed questions raised by Uwe: TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 UDELAY_TSC Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in the mainboard Kconfig. The remaining question of Uwe's is a deeper problem: --- We'll have to check if this works. From a quick glance the Rumba does not have the mmx related lines (which _are_ in Makefile.romccboard.inc, though): crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc --- We're going to need a whole variant of this standard mainboard OR we're going to have to make (some) of the unconditional includes above conditional. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29Fixes per Uwe's comments.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28This is the beginning of support for Geode and Kconfig in v2. Ronald G. Minnich
It also brings in the vsm from v3, which was a much cleaner cut. Over time, I hope to bring all the code back from v3. I have some rumbas at home and want to use them. I have a patch which comes in next that makes the rumba build. Note that I am holding the src/*/amd/Kconfig patch until these get merged. These have no impact on the current system. Note that this is not complete but I want to fill in the blanks bit by bit. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28Move DCACHE support into the cpu family for AMD model_fxx.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27Added support for the AMD S1G1 socket in kconfigCristi Magherusan
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27Clean up some DCACHE related options.Patrick Georgi
In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a boolean value, so make it so. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Add microcode to socket_940 and socket_F. Part of the last reverting commit.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Revert socket abstraction.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Add support for AMD Socket 940. Move common files to model_fxx.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Add kconfig support for ASUS P2B-F.Uwe Hermann
Only build-tested so far, not tested on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Fix copy-paste error in src/cpu/x86/Kconfig.Uwe Hermann
That file defines XIP_ROM_BASE twice, but the latter definition should be XIP_ROM_SIZE (not *_BASE). These exact two definitions are listed in src/Kconfig already, though, so maybe one of the two locations should remove them? Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25Various Kconfig and Makefile.inc fixes and cosmetics.Uwe Hermann
- Whitespace fixes, remove trailing whitespace, use TABs for identation (except in Kconfig "help" lines, which start with one TAB and two spaces as per Linux kernel style) - Kconfig: Standardize on 'bool' (not 'boolean'). - s/lar/cbfs/ in one Kconfig help string. - Reword various Kconfig menu entries for a more usable and consistent menu. - Fix incorrect comment of NO_RUN in devices/Kconfig. - superio/serverengines/Kconfig: Incorrect config name. - superio/Makefile.inc: s/serverengine/serverengines/. - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/. - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string. - mainboard/via/epia-n/Kconfig: Fix "bool" menu text. - console/Kconfig: Don't mention defaults in the menu string, kconfig already displays them anyway. - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24Add support for AM2 CPUs (I fixed the 0x11 issue).Myles Watson
Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24The variable is already checked when including the socketF subdirectory.Myles Watson
Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24This patch is about the DA-C2 and RB-C2. Chip with install processorZheng Bao
Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied to them are almost the same. Issues: 1. I really dont know what their nicknames are (Shanghai C2 or something). 2. About the mc_patch_01000086.h, I dont know if it is allowed to be released. If you really need it, please contact AMD Inc to see if it is public. 3. My RB-C2 is Socket type AM3, which needs DDR3 support. Probably your RB-C2 doesnt need DDR3. If it does and you really need it, please contack AMD Inc to see if it is allowed to release DDR3 code. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-21Change the intel cpu makefile.inc so that it fits the model better.Ronald G. Minnich
- intel/Makefile.inc only mentions sockets - those sockets are conditionally included - makefile.inc in socket directories are almost all unconditionally included - Get rid of if where possible, use -$(CONFIG_VARIABLE) instead as per Kconfig standards in linux kernel See the Kconfig.tex documentation for questions. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-20This goes a surprisingly long way to building the epia-n. It also hasRonald G. Minnich
important corrections to the Kconfig and Makefile.inc that were there. I would like to go ahead and get this in, because I don't want anyone to continue using what is in the upstream tree as it now exists. I also tested old-style build with this and it did not break anything. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-13- AMD selected a couple of options that are incompatible with QEmu (andPatrick Georgi
probably others). Only select them for AMD - Make the bootblock smaller (only one copy of it), and don't pad the bootblock using dd(1), but top-align inside cbfstool, to reduce dependencies on unix tools. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-13Fix some conflicting types of variablesPatrick Georgi
Remove the normal/* files from the image. they're just copies of fallback/* anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12This now builds. Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Fix multiple missing files and errors from the recent commit. This happenedRonald G. Minnich
when Patrick's tree and mine got out of sync. Link stage still fails. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Kconfig!Patrick Georgi
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11cpu/amd/model_lx used its own routine for copying coreboot_ram. ThisPatrick Georgi
change makes it use the generic infrastructure. NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram, this change has a high probability to break that place - so look into it. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA ↵Zheng Bao
should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-22Don't put .o files in the source tree. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21this bug sneaked in during conversionStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21add intel speedstep support and some PM fixes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21* rework tsc based timer code to use inb instead of outb for calibrationStefan Reinauer
* Add generic Local APIC based timer code. This timer does not need expensive calibration and thus reduces the boot time by up to more than a second. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18coding style fixes for powernow (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17Bring S1g1 cpu names up to date with the officialWard Vandewege
Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data from Table 9. Build tested. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17Bring Socket F cpu names up to date with the officialWard Vandewege
Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data from Table 7. Build tested. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17Bring AM2 cpu names up to date with the officialWard Vandewege
Revision Guide for AMD NPT Family 0Fh Processors Rev. 3.42 March 2009, found at http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf This patch takes its data from Table 8. Build tested, and boot tested on a AMD Athlon(tm) Dual Core Processor 5050e. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10Apparently I'm not the only one who forgets which way the outb andEd Swierk
outl arguments go. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02Move the v3 resource allocator to v2.Myles Watson
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Add support for the Intel Eagle Heights development board.Thomas Jourdan
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Fix typo and only output post code if the work was done.Myles Watson
Thanks to Thomas Jourdan <thomas.jourdan@gmail.com> for reporting it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Add AMD family 10 AM2r2 support.Zheng Bao
Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is. This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE. It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-21This patch adds a proper namestring generation to our ACPIgen generator.Rudolf Marek
Its used for Name and Scope and Processor now. As bonus, it allows to create a multi name paths too. Like Scope(\ALL.YOUR.BASE). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17Patch AMD Fam10 C2 for errata 327, 344, 346, 354, 351.Marc Jones
Removed c2 HT Phy 520a/530a reserved bit. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16Maximilian Thuermer found a bug where the HT link capability code was alwaysMarc Jones
updating the passed value to the next link offset even when it was on the requested link (cap_count). Maximilian also found a bug where the linktype was still getting attributes even when it wasn't initialized. This should fix the HT problems for Fam10 C2. There are still issues with the microcode which need to be resolved. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06Fix for Erratum 343 for AMD Fam10h CPUs.Marco Schmidt
Signed-off-by: Marco Schmidt <mashpb@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03Revert "CMOS: Add set_option and rework get_option."Luc Verhaegen
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660. Stepan pointed out that "s" means string, which makes the following statement in this commit message invalid: "Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go." Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03CMOS: Add set_option and rework get_option.Luc Verhaegen
To ease some of my debugging pain on the unichrome, i decided i needed to move FB size selection into cmos, so i could test a size and then reset it to the default after loading this value so that the next reboot uses the (working) default again. This meant implementing set_option in parallel to get_option. get_option was then found to have inversed argument ordering (like outb) and passing char * and then depending on the cmos layout length, which made me feel quite uncomfortable. Since we either have reserved space (which we shouldn't do anything with in these two functions), an enum or a hexadecimal value, unsigned int seemed like the way to go. So all users of get_option now have their arguments inversed and switched from using ints to unsigned ints now. The way get_cmos_value was implemented forced us to not overlap byte and to have multibyte values be byte aligned. This logic is now adapted to do a full uint32_t read (when needed) at any offset and any length up to 32, and the shifting all happens inside an uint32_t as well. set_cmos_value was implemented similarly. Both routines have been extensively tested in a quick separate little program as it is not easy to get this stuff right. build_opt_tbl.c was altered to function correctly within these new parameters. The enum value retrieval has been changed strol(..., NULL, 10) to stroul(..., NULL, 0), so that we not only are able to use unsigned ints now but so that we also interprete hex values correctly. The 32bit limit gets imposed on all entries not marked reserved, an unused "user_data" field that appeared in a lot of cmos.layouts has been changed to reserved as well. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27Move coreboot_ram and coreboot_apc to CBFS. This allows to Patrick Georgi
reduce the size of the bootblock (done for kontron/986lcd-m) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14Update equivalent processor revision ID to load latest microcode patches andMarc Jones
register setting for all FAM10 processors. This does not include new errata for FAM10 C2. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Vincent Lim (vincent.lim@amd.com) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11This patch adds high table support to qemu. It was already added toMyles Watson
src/northbridge/intel/i440bx/ but not to src/cpu/emulation/qemu-x86/northbridge.c It also adds a driver for the ISA device that is found when using 0.9.1 If you look in a log without this patch you won't find the RTC init lines. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-10 05:34:36 +0000