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2014-08-06Set armv7 up for cpu_info to work as on x86 (so threads can work)Ronald G. Minnich
On x86, cpu_info lives at the top of stack. Make the arm do that as well, as the threading model needs that and so will multicore support. As part of this change, make the stack size a power of 2. Also make it much smaller -- 2048 bytes is PLENTY for ram stage. Note that the small stack size is counterintuitive for rom stage. How can this work in rom stage, which needs a HUGE stack for lzma? The main use of STACK_SIZE has always been in ram stage; since 2002 or so it was to size per-core stacks (see, e.g., src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE and, more recently, thread stacks. So, we define the STACK_TOP for rom and ram stage, but the STACK_SIZE has no real effect on the ROM stage (no hardware red zones on the stack) and hence we're ok with actually defining the "wrong" stack size. In fact, the coreboot_ram ldscript for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc Observed stack usage in ramstage: BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1 Jumping to boot code at 23104044 CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes entry = 23104044 Which means we do need 2K, not 1K. Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66135 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6501 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-05exynos5420: get rid of old exynos5420_config_l2_cache()David Hendricks
We set up L2 cache early in romstage now so the old function is now redundant. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef Reviewed-on: https://gerrit.chromium.org/gerrit/65428 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f) exynos: stack size: Increase the stack size to 16KB. The lzma decoding function in the RAM stage allocates nearly 16KB on the stack which is shared between the bootblock, rom stage, and ram stage. The stack had been much too small and needed to be expanded. Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65937 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b) exynos: gpio: add a bigger delay when reading board strappings Z-state pins were not reading reliably with a 5us delay, so increase it to 15us. This is ported from https://gerrit.chromium.org/gerrit/64338 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35 Reviewed-on: https://gerrit.chromium.org/gerrit/65727 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084) exynos5420: enable DMC internal clock gating lets enable memory controller internal clock gating for ddr3. with these bits enabled we save some power out of ddr3. This is ported from https://gerrit.chromium.org/gerrit/#/c/60774 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f Reviewed-on: https://gerrit.chromium.org/gerrit/65728 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781) exynos5420: Correct the 600MHz PMS value In UM ver0.02, 600MHz clock PMS values differs from what is programed currently. Though this also results in 600MHz clock, but it is better to match what UM says. This patch chnage this as per UM This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3 (Note: we already used the correct 600MHz value for KPLL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5 Reviewed-on: https://gerrit.chromium.org/gerrit/65726 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f) Squashed five commits pertaining to exynos. Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6425 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04cpu/intel: Fix out-of-bounds read due to off-by-one in conditionEdward O'Callaghan
If power_limit_1_time > 129 is false then power_limit_1_time can have a value of up to 129 leading to an out-of-bounds illegal read indexing the power_limit_time_sec_to_msr[] array. Thankfully all call sites have been doing the right thing up until now so the issue has not been visible. Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6478 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03cpu/x86/lapic/lapic.c: trivial: fix comment on #elseDaniele Forsi
The preprocessor symbol has only one "L". Change-Id: I3ec302f18d3bcc81bb45a9d53140f8aedd019317 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6469 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31timer: Add functions to initialize absolute timer structures.Gabe Black
Otherwise there's no good way to create an absolute timer structure without fiddling with its internal structure or assuming a zero initialized structure has a value of zero. Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a) exynos: Simplify the monotonic timer implementation. The previous implementation was overly complicated, and when used in the timestamp implementation produced some weird and broken results. Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65302 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557) Squashed two closely related commits. Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6406 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31armv7/exynos5420: Configure CPU cores for kernel to enable SMP.Hung-Te Lin
The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30model_206ax_init.c: Trivial - fix indentEdward O'Callaghan
Change-Id: I84876c95522fca5560bcbc8e81dfcb09faf3b326 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6412 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-30cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)Martin Roth
This adds the CPU initialization pieces for Intel's Atom C2000 processor (Formerly Rangeley). Change-Id: I77d69f42c959bbc294784f044b7b0dcc2e30f30c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6368 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30model_fxx/processor_name.c, hudson/lpc.c: add missing break statementsDaniele Forsi
Found by Cppcheck 1.65. Fixes: (warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing? (warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing? Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30cpu/intel/model_2065x/model_2065x_init.c: Remove dead codeEdward O'Callaghan
Unused array is dead code. Spotted by Clang build. Change-Id: I11397716b39de08f1226413019e3beeeeaac6149 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6131 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
Based on damo22's work and my X230 tracing. Works for my X230 in a variety of RAM configs. Also-By: Damien Zammit <damien@zamaudio.com> Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5786 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Drop get_bus_conf.c filesKyösti Mälkki
The only remaining purpose for get_bus_conf() was to fill in obscure bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete enumeration is available in devicetree and PCI configuration space so discard these arrays. Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6360 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()Kyösti Mälkki
Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6357 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Drop some excessive agesawrapper.h includesKyösti Mälkki
Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6262 Tested-by: build bot (Jenkins)
2014-07-24AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()Kyösti Mälkki
Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6355 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-23cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`Paul Menzel
Change-Id: I91cd84d155a2cb1200cb82c31256cfa743e8ea9b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6227 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-23src/.../Kconfig: various small fixes to textsDaniele Forsi
Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-19intel/model_2065x: Remove dead code.Vladimir Serbinenko
nehalem uses gm45-like approach to resume backup so this code is never used. Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5975 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-17cpu,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6286 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17misc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6296 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14AGESA fam15: Fix entry to cimx/sb900Kyösti Mälkki
Move SB900 call to match comments and changes already made for family14 et al. Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6238 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA CIMx: Move late init out of get_bus_conf()Kyösti Mälkki
Followup deals further with Fam15 case. For unknown reasons calls were commented out for amd/dinar and they remain that way. Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Trace execution with AGESAWRAPPER()Kyösti Mälkki
Implement logging just once to have uniform output. Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6180 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AMD SPI: Optimise for longer writesKyösti Mälkki
Leave it to the implementation of flash->write() to split the writes to match SPI controller and SPI flash part restrictions. This allows for some optimisation for auto-address-increment (AAI) commands. Kconfig AMD_SB_SPI_TX_LEN can be kept as local. Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6164 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-11src: Make use of 'CEIL_DIV(a, b)' macro across treeEdward O'Callaghan
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10intel/haswell: add vmx support w/Kconfig optionMatt DeVillier
patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx tested/verified working on google/panther Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6223 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-08cpu: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6207 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05Drop redundant select CACHE_AS_RAMKyösti Mälkki
The few remaining boards without CAR override this with select ROMCC. Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6172 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6135 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-03AGESA: Call get_bus_conf() just onceKyösti Mälkki
Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Add agesawrapper_post_device()Kyösti Mälkki
NOTE: The procedure is moved across a collected timestamp TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted for in an earlier entry in cbmem -t output. Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6132 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the build of romstage also for boards without HAVE_ACPI_RESUME. These symbols got exposed as the use of preprocessor directives was reduced. We expect the linker to do a fair job and optimize away function bodies that are on unreachable execution paths. Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6067 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Clean separation of SPI flashKyösti Mälkki
To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6085 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-03AGESA boards: Add prepare_for_resume()Kyösti Mälkki
Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6084 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03AGESA S3: Refactor S3 backup store locations in SPIKyösti Mälkki
Prepare code to locate S3 backup from CBFS as a file. Follow-up will replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content(). Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6083 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-30x86 MTRR: Drop unused return valueKyösti Mälkki
It was never well-defined what value this function should return. Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30Use MTRR definesKyösti Mälkki
Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6123 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always falseEdward O'Callaghan
Comparison of unsigned expression < 0 is always false. Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII artEdward O'Callaghan
Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6154 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-28Don't add .eh_frame sections to SMM imagePatrick Georgi
We don't need exception handlers and they waste space. Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6105 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-25AGESA: Move config parameters for non-volatile S3 dataKyösti Mälkki
These parameters are not specific to the southbridge device, but the implementation of S3 storage defined by CPU code. Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6081 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25Declare acpi_is_wakeup_early() only onceKyösti Mälkki
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21cpu/amd/agesa: Use acpi_is_wakeup()Kyösti Mälkki
Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I6ad5fb7e32c59be7d84f28461c238c3975e1e04e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6078 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6072 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-17intel/model_2065x: Add 20652 microcode.Vladimir Serbinenko
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5117 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-06AGESA: Use common heap allocatorKyösti Mälkki
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5689 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
realpath and readlink can be used to do the same thing - in this case we're turning path1/path2/../path3/path4 into path1/path3/path4 so that the makefile's wildcard routine can evaluate it. Debian derivatives don't seem to include realpath. (and even when it's installed, it's not the gnu coreutils version.) Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5793 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 12:32:56 +0000