coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-11-12	Initialize the VMX MSR	Marc Jones
2012-11-12	Revert "Remove code that enables/disables VMX in coreboot on chromebooks."	Marc Jones
2012-11-12	sandybridge: Correct reporting of cores and threads	Stefan Reinauer
2012-11-07	Leave power control registers unlocked	Sameer Nanda
2012-11-06	cpu/intel/model_1067x: Add proper c-state/p-state/thermal support	Nico Huber
2012-11-06	intel/socket_BGA956: enable speedstep, CAR, MMX, SSE	Patrick Georgi
2012-11-05	Overhaul speedstep code	Nico Huber
2012-11-05	Fix some indentation flaws and break very long lines	Nico Huber
2012-11-02	AMD agesa: add enable cache at the end of disable_cache_as_ram	Siyuan Wang
2012-11-02	Correct FSB reading in speedstep ACPI	Nico Huber
2012-11-01	Merge cpu/intel/acpi.h into cpu/intel/speedstep.h	Nico Huber
2012-10-30	Add support for socket LGA775	Stefan Tauner
2012-10-07	Fix typo in mPGA603 socket	Kyösti Mälkki
2012-10-07	Remove chip.h files without config structure	Kyösti Mälkki
2012-09-19	C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C3...	Siyuan Wang
2012-09-05	VIA Nano: Add support for VIA Nano CPUs	Alexandru Gagniuc
2012-09-05	buildsystem: Make CPU microcode updating more configurable	Alexandru Gagniuc
2012-08-27	Intel model_106cx: change CAR to HT-capable	Kyösti Mälkki
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-08-09	Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU	Kyösti Mälkki
2012-08-09	AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution	Kyösti Mälkki
2012-08-09	Synchronize rdtsc instructions	Stefan Reinauer
2012-08-07	Move cpus_ready_for_init() to AMD K8	Kyösti Mälkki
2012-08-05	AMD S3: Remove the hardcoded volatile position	zbao
2012-08-04	Make the device tree available in the rom stage	Stefan Reinauer
2012-08-03	Intel CPUs: Fix counting of CPU cores	Kyösti Mälkki
2012-08-01	Intel Sandybridge: add reserved memory as resources	Kyösti Mälkki
2012-07-31	Revert "Use broadcast SIPI to startup siblings"	Sven Schnelle
2012-07-31	Revert "remove CONFIG_SERIAL_CPU_INIT"	Sven Schnelle
2012-07-26	CPU: Add option to set TCC activation offset	Duncan Laurie
2012-07-26	ACPI: Add a method to notify OS to re-read _PPC	Duncan Laurie
2012-07-26	ACPI: Add function to write _PPC using NVS	Duncan Laurie
2012-07-26	USBDEBUG: buffer up to 8 bytes	Sven Schnelle
2012-07-26	Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs	Stefan Reinauer
2012-07-26	Enable Microcode in CBFS for all SandyBridge/IvyBridge systems	Stefan Reinauer
2012-07-25	SMM: Fix state table for Intel Core2 CPUs	Stefan Reinauer
2012-07-25	Fix comment to reference IvyBridge, too	Stefan Reinauer
2012-07-25	Include SandyBridge Microcode when IvyBridge is enabled	Stefan Reinauer
2012-07-25	Fix date output in Microcode update	Stefan Reinauer
2012-07-25	Fix LAPIC timer on Ivy Bridge systems	Stefan Reinauer
2012-07-24	CPU: Set flex ratio to nominal TDP ratio in bootblock	Duncan Laurie
2012-07-24	SMM: Fix state save map for sandybridge and TSEG	Duncan Laurie
2012-07-24	SMM: Add heap region and move C handler higher in region	Duncan Laurie
2012-07-24	CPU: Update ivybridge PP1 current limit value	Duncan Laurie
2012-07-24	CPU: Add basic support for Nominal Configurable TDP	Duncan Laurie
2012-07-24	Rename cache_lbmem() to cache_ramstage()	Stefan Reinauer
2012-07-24	Config changes to support microcode in CBFS	Vadim Bendebury
2012-07-24	Add microcode blob processing	Vadim Bendebury
2012-07-24	Add code to read Intel microcode from CBFS	Vadim Bendebury
2012-07-24	Make MAX_PHYSICAL_CPUS invisible on non-AMD boards	Stefan Reinauer