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2018-10-31reset: Finalize move to new APINico Huber
Move soft_reset() to `southbridge/amd/common/` it's only used for amdfam10 now. Drop hard_reset() for good. Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-29x86/mp_init: Add configurable stack size for SMM relocateMarshall Dawson
A stack overrun has been observed on AMD64 CPUs during the SMM module relocation process. Change the assumed required size from equaling the save structure's size to a Kconfig symbol. A value of 0x400 doubles the size used by AMD64 systems and maintains the size used by EM64T. BUG=b:118420852 TEST=S3 on Grunt and verify 0x2f000-0x30000 uncorrupted Change-Id: Ib1d590ee4afb06ca649afd6ad253cdfd969ae777 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-24cpu/intel/smm: Don't make assumptions on TSEG_SIZEArthur Heymans
Do not assume: - TSEG is 8M - IED_REGION_SIZE is set (not needed on older platforms). Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27872 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19{cpu,drivers}/amd: Replace MTRR addresses with macrosElyes HAOUAS
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29173 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/x86/smm: Fix non-local header treated as localElyes HAOUAS
Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-10-04cpu/intel/car: Fix typoElyes HAOUAS
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-26cpu/intel/model_206ax: detect number of MCE banksDan Elkouby
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset only 7. This causes Linux to spuriously log errors during boot and S3 resume. Fix this by reading the real value from the right MSR. Change-Id: Id05645009259fd77b4de49bde518361eeae46617 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/28443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-25src/cpu/via/nano: Remove unneeded includeElyes HAOUAS
Change-Id: I656b11add77012271ccc0c80dfcf97d20937dba2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-18cpu/*/car: fix ancient URL explaining XIP range run-time calculationStefan Tauner
Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-06qemu-q35: Use the TSC for udelayMichael van der Westhuizen
Use the TSC for delays on q35, ensuring that the TSC delay code is included in the correct stages when selected. Tested on qemu-35 and wedge-100s (for no regressions). Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Signed-off-by: Michael van der Westhuizen <rmikey@fb.com> Reviewed-on: https://review.coreboot.org/28526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-20cpu/intel/common: add function to init cppc_configMatt Delco
This change adds a method to init a cppc_config structure in a way that should ideally work across Intel processors that support EIST. Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-17intel/socket_mPGA604: Keep only model f2xKyösti Mälkki
The only board left in the tree (aopen/dxplplusu) with this socket is the slower of the mPGA604 variants with FSB 533. Change-Id: I04707a0dcb8f5b6235ead8c02ddfddfe7c3b8b1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/28116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-13src: Get rid of non-local header treated as localElyes HAOUAS
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13cpu/intel/car: Align the stack to 16 bytes before romstage_mainArthur Heymans
Change-Id: I1415c18779bc481fdec5f72f83c06a58ce6d5c39 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26797 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13cpu/x86/smm/smm_module_loader.c: Avoid static analysis error "unused value"Richard Spiegel
In procedure smm_load_module, variables fxsave_size and fxsave_area are set to 0 and NULL, but if CONFIG_SSE is enabled, they are overwritten. Change the code setting the value to an "else" of the "if" testing CONFIG_SSE, thus avoiding static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I3042b037017a082378b53ee419c769c535632038 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09cpu/x86/mp_init.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure save_bsp_msrs, the structure pointer "msr_entry" is updated every time procedure save_msr() is called. However, after the last call of save_msr(), "msr_entry" is not used, thus causing a static analysis error. Add a "(void)msr_entry;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0fb336fbf49eec3da255fadbe38b3a38768d0cf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/cpu: Fix typoElyes HAOUAS
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09cpu/x86/mp_init.c: Fix error treatmentRichard Spiegel
In procedure allocate_cpu_devices(), if structure pointer new is null skip using the pointer. Add a "continue;" to skip using the pointer. The issue was found by static analysis tool. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7011fbfa0725f22a6dfbca6752e668eddac3463c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27951 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/intel/smm: Make sure SMRR base is aligned to SMRR sizeArthur Heymans
If TSEG_BASE is not TSEG_SIZE aligned the SMRR settings are invalid, therefore guard against this. Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Improve formattingMarshall Dawson
Remove for() braces from around single lines. Remove extra blank lines. This cleans up checkpatch problems in a subsequent patch. Change-Id: I329ac03365e51799581c56eed27ee54de6826f14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Rename MCA status registerMarshall Dawson
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-06mp_init: fix typoRaul E Rangel
BUG=none TEST=none Change-Id: Ic2d7bf5f5335894ede98dc7e6cc6a65e4897e487 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-03cpu/x86/lapic/apic_timer.c: Compile the same code for all stagesArthur Heymans
timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment. Clean up the code paths by employing CAR_GLOBAL for the global state which allows the same code to be used in all stages. Change-Id: I08fd1795508f76abdab1618585366bf9d06482ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27801 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067xArthur Heymans
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-30cpu/intel/microcode: Add helper functions to get microcode infoRizwan Qureshi
Add 4 helper functions to get microcode info. * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. The simpler thing would be to just move the struct microcode to microcode.h so that the structure members can be dereferenced. To encapsulate the structure details added the helper functions. This information will be used in future to compare microcodes for update. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27365 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
* Add a function to return CPU platform ID bits * Add a function to return platform type ** Platform id is 4 on Lenovo T430 (mobile) ** Platform id is 1 on HP8200 (desktop) * Use introduced method to handle platform specific code * Use enum for platform type * Report platform ID Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-28smm: Add canary to end of stack and die() if a stack overflow occursRaul E Rangel
If CPU 0's stack grows to large, it will overflow into CPU 1's stack. If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop. When the stack overflow occurs it will override the return pointer for CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return to a random address. This method is not foolproof. If code allocates some stack variables that overlap with the canary, and if the variables are never set, then the canary will not be overwritten, but it will have been skipped. We could mitigate this by adding a larger canary value if we wanted. I chose to use the stack bottom pointer value as the canary value because: * It will change per CPU stack. * Doesn't require hard coding a value that must be shared between the .S and .c. * Passing the expected canary value as a parameter felt like overkill. We can explore adding other methods of signaling that a stack overflow had occurred in a follow up. I limited die() to debug only because otherwise it would be very hard to track down. TEST=built on grunt with a small and large stack size. Then verified that one causes a stack overflow and the other does not. Stack overflow message: canary 0x0 != 0xcdeafc00 SMM Handler caused a stack overflow Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27229 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-27smm: Switch from %edx to %ebxRaul E Rangel
%edx gets clobbered before the c handler is invoked. This is just a cleanup cl to make the next cl look clean. BUG=b:80539294 TEST=verified SMI still works on grunt. Change-Id: I21bf41ed4fdeaaa8737c883f202a39cb57c2b517 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27228 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-27smm: Push a null stack base pointerRaul E Rangel
When generating a backtrace we need an indicator when we have hit the beginning of the stack. The i386 ABI states that %ebp points to the next stack frame. NULL can be used to indicate the end of the stack. We could add a NULL return pointer at %ebp+4, but I decided to omit it since a NULL stack pointer can be used as an indicator that there is no return pointer. BUG=b:80539294 TEST=built and tested on grunt Change-Id: I8a48114d31a5c716335d264fa4fe4da41dc5bf11 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27226 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-27smm: Make local variables relative to ebpRaul E Rangel
This reduces the cognitive overhead of referencing locals via esp since it changes with every push. BUG=b:80539294 TEST=built and booted on grunt. Change-Id: Ib7eb98ce3483d4fc803696c1b2496d8384317536 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-27smm: Clear SMRAM when debuggingRaul E Rangel
This makes it easier to spot unused RAM. BUG=b:80539294 TEST=built and tested on grunt. Verified unused memory was set to 0xcdcdcdcd Change-Id: I335eaf642bd8526f31819eaac95ce80c2df3c300 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-27cpu/intel/p4-netburst: skip caching rom on model_fxxArthur Heymans
An unidentified combination of speculative reads and branch predictions inside WRPROT-cacheable memory can cause invalidation of cachelines and loss of stack on models based on NetBurst microarchitecture. Therefore disable WRPROT region entirely for all family F models. As an extreme example, just changing the location of a constant string passed to printk() has been witnessed to make a the boot fail early on in romstage. Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-27x86/car: Replace reference of copy_and_run locationKyösti Mälkki
For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
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