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Some coreboot project code with my work
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Age
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Author
2012-04-06
Add Sandybridge/Cougar Point support to SMM relocation handler
Stefan Reinauer
2012-04-06
Cache 8MB flash instead of 4MB
Stefan Reinauer
2012-04-05
Fix timer frequency detection on Sandybridge
Stefan Reinauer
2012-04-05
Invalidate cache before first jump
Stefan Reinauer
2012-04-05
Update documentation in smmrelocate.S to mention TSEG
Stefan Reinauer
2012-04-05
Add support for Intel Sandybridge CPU
Stefan Reinauer
2012-04-04
Add support to run SMM handler in TSEG instead of ASEG
Stefan Reinauer
2012-04-03
Add support for Intel Turbo Boost feature
Stefan Reinauer
2012-04-02
Apply cache-as-ram conditionally on socket mPGA604
Kyösti Mälkki
2012-04-02
S3 code whitespaces changes.
zbao
2012-03-31
Whitespace fixes
Patrick Georgi
2012-03-31
Intel cpus: get MAXPHYADDR at runtime for new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: add hyper-threading CPU support to new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: improve CPU compatibility of new CAR
Kyösti Mälkki
2012-03-31
Add support for RAM-less multi-processor init
Kyösti Mälkki
2012-03-31
Intel cpus: apply some good programming practices in new CAR
Kyösti Mälkki
2012-03-31
Intel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki
2012-03-31
Intel cpus: copy model_6ex CAR code
Kyösti Mälkki
2012-03-30
Make MTRR min hole alignment 64MB
Duncan Laurie
2012-03-30
Fix MB calculation in the reporting of the MTRR hole
Duncan Laurie
2012-03-30
MTRR: add alternate allocation method for odd memory maps
Duncan Laurie
2012-03-30
Add Kconfig options to enable TSEG and set a size
Duncan Laurie
2012-03-30
drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
Stefan Reinauer
2012-03-30
Add an option to keep the ROM cached after romstage
Stefan Reinauer
2012-03-25
Fix possible deadlock on SMP stop_this_cpu
Kyösti Mälkki
2012-03-25
Intel cpus: Fix deadlock on hyper-threading init
Kyösti Mälkki
2012-03-17
Intel cpus: Include CAR from socket
Kyösti Mälkki
2012-03-16
Rename AMD_AGESA to CPU_AMD_AGESA
Kyösti Mälkki
2012-03-16
Fix AMD Agesa leaking Kconfig
Kyösti Mälkki
2012-03-16
ROMCC boards have no XIP limit
Patrick Georgi
2012-03-16
Via Epia-N and C3: Set ioapic delivery type in Kconfig
Patrick Georgi
2012-03-16
Fix address of IDT in real-mode entry
Kyösti Mälkki
2012-03-09
move console includes to central console/console.h
Stefan Reinauer
2012-03-07
Move C labels to start-of-line
Patrick Georgi
2012-02-20
Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
Marc Jones
2012-02-17
Remove whitespace.
Patrick Georgi
2012-02-16
AGESA F15: AGESA family15 model 00-0fh cpu wrapper
Kerry Sheh
2012-02-16
Intel cpus: use CPU_PHYSMASK_HI define in CAR
Kyösti Mälkki
2012-02-15
Intel model_106cx: Use symbolic names for MTRR bits
Kyösti Mälkki
2012-02-13
AMD Geode cpus: apply un-written naming rules
Kyösti Mälkki
2012-02-10
Intel cpus: apply un-written naming rules
Kyösti Mälkki
2012-02-09
Add Intel Socket LGA771
Sven Schnelle
2012-02-09
VIA cpus: apply un-written naming rules
Kyösti Mälkki
2012-01-23
post code: Replaced hard-coded post code with macro
Vikram Narayanan
2012-01-21
trivial: spelling fixes in comments
Vikram Narayanan
2012-01-20
Leave SSE and MMX instructions enabled in coreboot
Stefan Reinauer
2012-01-10
MTRR: get physical address size from CPUID
Sven Schnelle
2012-01-09
Fix Geode GX2 + LX caching for tiny bootblock.
Nils Jacobs
2012-01-09
ACPI: mark empty get_cst_entries() weak
Sven Schnelle
2011-12-26
Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
Marc Jones
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