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broadwell_refcode
e6230
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Some coreboot project code with my work
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Age
Commit message (
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Author
2016-07-26
intel car: Use MTRR WRPROT type for XIP cache
Kyösti Mälkki
2016-07-26
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Kyösti Mälkki
2016-07-23
intel/haswell: Remove useless MTRR clear
Kyösti Mälkki
2016-07-23
intel/haswell post-car: Minor fix on MTRR setting
Kyösti Mälkki
2016-07-23
intel/haswell: Add asmlinkage for romstage_after_car()
Kyösti Mälkki
2016-07-22
cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundary
Aaron Durbin
2016-07-22
intel car: Unify postcodes
Kyösti Mälkki
2016-07-22
intel car: Unify whitespace and comment fixes
Kyösti Mälkki
2016-07-22
intel car: Remove guard on XIP_ROM_SIZE
Kyösti Mälkki
2016-07-22
intel model_106cx: Include CAR from socket directory
Kyösti Mälkki
2016-07-21
AMD k8 fam10: Fix CAR GLOBALS late in romstage
Kyösti Mälkki
2016-07-15
AMD binaryPI: Use common romstage ram stack
Kyösti Mälkki
2016-07-15
AMD binaryPI: Split romstage ram stack
Kyösti Mälkki
2016-07-15
AMD binaryPI: Use common ACPI S3 recovery
Kyösti Mälkki
2016-07-15
AGESA: Use common romstage ram stack
Kyösti Mälkki
2016-07-15
AGESA: Use common ACPI S3 recovery
Kyösti Mälkki
2016-07-10
intel post-car: Consolidate choose_top_of_stack()
Kyösti Mälkki
2016-07-10
AMD k8 fam10: Drop excessive spinlock initialization
Kyösti Mälkki
2016-07-10
AMD k8 fam10: Fix romstage handoff
Kyösti Mälkki
2016-06-29
AMD k8 fam10: Refactor S3 recovery
Kyösti Mälkki
2016-06-29
intel/haswell: No need for ACPI S3 resume backup
Kyösti Mälkki
2016-06-29
intel romstage: Use run_ramstage()
Kyösti Mälkki
2016-06-24
region: Add writeat and eraseat support
Antonello Dettori
2016-06-22
ACPI S3: Add common recovery code
Kyösti Mälkki
2016-06-22
ACPI S3: Move SMP trampoline recovery
Kyösti Mälkki
2016-06-22
Ignore RAMTOP for MTRRs
Kyösti Mälkki
2016-06-22
intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-22
intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-22
intel cache-as-ram: Fix comment about MTRRs
Kyösti Mälkki
2016-06-21
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-21
intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-21
intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-20
amd/fam_10h-fam_15h: allow building without microcode updates
Arthur Heymans
2016-06-20
amd/geode: Fix comment about ACPI S3
Kyösti Mälkki
2016-06-20
VIA C7 NANO: Fix early MTRR setting
Kyösti Mälkki
2016-06-18
intel: Fix romstage main() with asmlinkage
Kyösti Mälkki
2016-06-18
intel/cache_as_ram_ht.inc: Fix include
Kyösti Mälkki
2016-06-18
intel cache_as_ram: Fix typo in comment
Kyösti Mälkki
2016-06-17
intel/model_206ax: Move platform specific defines
Kyösti Mälkki
2016-06-17
Move definitions of HIGH_MEMORY_SAVE
Kyösti Mälkki
2016-06-17
Fix some cbmem.h includes
Kyösti Mälkki
2016-05-18
AGESA vendorcode: Build a common amdlib
Kyösti Mälkki
2016-05-17
intel/sch: Merge northbridge and southbridge in src/soc
Stefan Reinauer
2016-05-12
AGESA f12: Build as libagesa.a
Kyösti Mälkki
2016-05-12
AGESA f16kb: Build as libagesa.a
Kyösti Mälkki
2016-05-09
drivers/uart: Use uart_platform_refclk for all UART models
Lee Leahy
2016-05-06
cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE
Aaron Durbin
2016-05-06
{cpu,soc}/intel: remove unused smm_init() function
Aaron Durbin
2016-05-06
cpu/x86/mp_init: reduce exposure of internal implementation
Aaron Durbin
2016-05-06
cpu/intel/haswell: convert to using common MP and SMM init
Aaron Durbin
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