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2020-01-18cpu/intel/model_6?x{slot_1}: Leave enabling CONFIG_SMP to the mainboardKeith Hui
These predate hyperthreading so they are not SMP capable unless installed in a SMP board. Turning SMP off shaves 128 compressed bytes from ramstage. Change-Id: I114bdc83ed40ccd9d3996aabf77422236d9d12fa Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27cpu/intel/microcode: Apply more strict guard for assembly filesKyösti Mälkki
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-26src/x86|cpu/intel: Hardcode FIT and IDMarshall Dawson
Revert two of the changes made in "arch|cpu/x86: Add Kconfig option for x86 reset vector" I6a814f7179ee4251aeeccb2555221616e944e03d The Intel FIT pointer and the ID section should be offsets from the top of flash, and aren't inherently tied to the reset vector or to bootblock. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26cpu/intel/car/p4-netburst: Add assert for SIPI_VECTOR_IN_ROMKyösti Mälkki
Location of _start16bit in entry16.inc is about to see some changes, lets make sure they don't break the alignment requirement here. Change-Id: Id8a0964982387e5321e8c89254922e1242cf85ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-20AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCKKyösti Mälkki
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20AGESA,binaryPI: Enable lapic early for udelay()Kyösti Mälkki
Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-20AGESA fam14: Remove early PCI subsystem ID settingKyösti Mälkki
Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-20AGESA fam14: Remove early p-state settingKyösti Mälkki
No improvement was measured with this applied. Change-Id: I99166e03f2580828c66305326f5141d956707f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37754 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-19arch/x86: Fix S3 resume without stage cacheKyösti Mälkki
It was possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Make it a three-way choice between different STAGE_CACHE options. For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer needed to have functional ACPI S3 resume and it is not allowed se use keyword select for symbols inside choice blocks. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
Change-Id: Iaa236f07aed52ccb8c4839047894a14a9446a109 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19arch/x86: Drop uses of ROMCC_BOOTBLOCKArthur Heymans
Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-19Drop ROMCC code and header guardsArthur Heymans
Change-Id: I730f80afd8aad250f26534435aec24bea75a849c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-18cpu/x86/mp_init: Fix typoElyes HAOUAS
Change-Id: Iee9cd3dc51937774b990bc6f9e00bb82e0132e76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37811 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-18src: Remove unused 'include <pc80/mc146818rtc.h>'Elyes HAOUAS
Change-Id: I72d7b83ef8c7f9b5b4b4376839279eff9b0a5f8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37484 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17cpu/intel: Remove ROMCC header guards and codeElyes HAOUAS
Intel's platforms use a GCC compiled bootblock. Change-Id: I779d7115fee75df9356873e9cc66d43280821812 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-13sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() callKyösti Mälkki
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-11AGESA, binaryPI: implement C bootblockMichał Żygowski
Modify CAR setup to work in bootblock. Provide bootblock C file with necessary C bootblock functions. Additionally chache the ROM and set the MMCONF base before jumping to bootblock main. Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11fmap: Make FMAP_CACHE mandatory if it is configured inJulius Werner
Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the pre-RAM FMAP cache code, there's no point in allowing the region to be optional anymore. This patch makes the section required by the linker. If a board doesn't want to provide it, it has to select NO_FMAP_CACHE. Adding FMAP_CACHE regions to a couple more targets that I think can use them but I don't know anything about... please yell if one of these is a bad idea and I should mark them NO_FMAP_CACHE instead. Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-06arch|cpu/x86: Add Kconfig option for x86 reset vectorMarshall Dawson
Prepare for an implementation supporting the reset vector in RAM and not the traditional 0xfffffff0. Add a Kconfig symbol that can be used in place of hardcoded values. Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04AGESA: Reduce S3_DATA_SIZEKyösti Mälkki
Make some room for C environment bootblock. The S3 resume feature needs less than 2 KiB. Change-Id: Ic49c313d492f1d18f59d61e84f81f106e3b41fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-30kill CAR_GLOBAL_MIGRATION leftoversArthur Heymans
Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37055 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30arch/*/*/early_variables.h: drop unused filesArthur Heymans
Kill off NO_GLOBAL_MIGRATION finally! Change-Id: Ieb7d9f5590b3a7dd1fd5c0ce2e51337332434dbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37054 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-30arch/x86/cache.h: Use ENV_CACHE_AS_RAM macroArthur Heymans
Change-Id: Ic7b088a04165bb24b9ebcebc1580a96ce0fdfcc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-30cpu/x86/tsc: Remove indirection when accessing mono_timer_gPatrick Georgi
Change-Id: Ice1426cec8f9c5d9644836b0cf025be50e932f48 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-29cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29cpu/x86/lapic/apic_timer.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: Ideac1a04d6bb1a5e9cc601be7bbfcebe56b4a5da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37050 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29cpu/x86/tsc/delay_tsc.c: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I0a1e9fcea54444a84cc0a6ac30fe7d053261bb1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37049 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29cpu/amd/{agesa,pi}/Kconfig: select SSE2Michał Żygowski
SSE2 instructions are supported by family14 and newer. SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27soc/intel/skylake: Clean up report_cpu_info() functionUsha P
This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 2. Make fill_processor_name function available in bootblock. 3. Reuse fill_processor_name. TEST= Succesfully able to boot soraka and verify the cpu_name "CPU: Intel(R) Pentium(R) CPU 4415Y @ 1.60GHz" Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36840 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-27binaryPI: Drop S3_DATA_POS and S3_DATA_SIZEKyösti Mälkki
Direct SPI flash manipulation is forbidden, need to go through respective FMAP and rdev APIs. Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37192 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-TSubrata Banik
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-25cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-25Drop superfluous C_ENVIRONMENT_BOOTBLOCK checksArthur Heymans
Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22cpu/intel/gen1/smmrelocate: Fix stale commentArthur Heymans
Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-22cpu/intel/smm: Drop em64t save stateArthur Heymans
This save state is just plainly wrong in many regards and em64t100 should be used. Checked with a model 0x17 core2 CPU. Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22cpu/x86/smm: Use PRIxPTR to print uintptr_tJacob Garber
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This fixes a compilation error when targeting x86_64 or using Clang 9.0.0. Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22cpu/amd/microcode: Remove microcode update routineKyösti Mälkki
This was only used with native amdfam10h-15h. Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21cpu/x86/lapic/lapic_cpu_init.c: Drop unused guardsArthur Heymans
Both model_2065x and model_206ax use the parallel mp init codepath. Change-Id: I6440d413761361ee8b69d5c76b69409bd7528b5d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37065 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21Kconfig: Remove not found sourcesElyes HAOUAS
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 01:30:33 +0000