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2015-11-23cpu/amd/fam15h: Set up Link Base Channel Buffer Count registersTimothy Pearson
Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12038 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-11-23cpu/amd: de-duplicate MSR include filesStefan Reinauer
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12510 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-22cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15hTimothy Pearson
Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12040 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to ↵Timothy Pearson
improve performance Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12039 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15hTimothy Pearson
Change-Id: I4cf6549234041c395a18a89332d95f20a596fc3e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12033 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22cpu/amd/family_10h-family_15h: Configure NB register 2Timothy Pearson
Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12032 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-21cpu/amd/car/post_cache_as_ram: Avoid trailing spacesPaul Menzel
Looking at the coreboot console logs there are sometimes trailing whitespaces in the output, for example, if writing `Done` was not possible. Adapt the code, that spaces are only added when needed. Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12357 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21amd/family_10h-family_15h: Fix poor performance on Family 15h CPUsTimothy Pearson
Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12028 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequenciesTimothy Pearson
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20cpu/amd/family_10h-family_15h: Fix incorrect revision detectionTimothy Pearson
The revision detection code for AMD Family 10h/15h was modified to use a 64-bit value instead of 32-bit in order to accomodate additional processor revisions. The FIDVID code was not updated at that point, leading to incorrect revision use during FIDVID. Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12026 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20nb/amd/amdfam10: Add HyperTransport probe filter supportTimothy Pearson
All modern Opteron processors support the HT probe filter, which helps to increase coherent fabric performance by reducing the number of HT transactions per cache probe. AMD recommends that the probe filter be enabled on all systems with more than two nodes, and it does not hurt to enable it on systems with 2 nodes. Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12021 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20cpu/amd/fam10h-fam15h: Set northbridge throttle valuesTimothy Pearson
The existing code did not set the northbridge throttle values on Family 15h, leading to sporadic and random deadlocks in the crossbar per AMD notes. Properly set the northbridge throttle values on Family 15h. Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12025 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-19cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDGTimothy Pearson
The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12022 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-16cpu/amd/fam10h-15h: Fix BSP stack corruption on 32-core Fam10 systemsTimothy Pearson
On some multi-socket AMD platforms there are too many cores for all APs to start up without stack collisions with either each other or the BSP. On such platforms a larger amount of CAR memory is also available. Allow the maximum DCACHE size to be increased via a mainboard- specific Kconfig flag. Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12015 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-15amd/model_fxx: Check FID&VID Support for the BSP (too)Urja Rannikko
Tested: Avoids crash with Sempron 2800+ on K8V-X. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12336 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
There were numerous issues surrounding AMD ECC initialization on Family 15h processors due to the incomplete derivation from Family 10h MCT code. Bring the Family 15h ECC initialization and supporting setup code in line with the BKDG recommendations. Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12003 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-14cpu/x86/lapic: Add stack overrun detectionTimothy Pearson
Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11cpu/amd: Add CC6 supportTimothy Pearson
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10cpu/amd/car: Add romstage BSP stack overrun detectionTimothy Pearson
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE Kconfig variable. There should be no functional difference between the existing code and the new code, however hardware verfication is encouraged on lesser used architectures such as AMD Geode. Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10cpu: Add a way to use microcode .h files back to the buildMartin Roth
The build was changed to remove usage of microcode .h files when all of the .h files were converted to binary. This is still needed for some builds when microcode binaries aren't in the blobs tree. Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12333 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-11-10amd/model_fxx: fix code style in FID&VID support checkUrja Rannikko
This is in AP code, fixed in preparation for copying the same check to BSP. Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12359 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-10cpu/intel: Add socket BGA1284Marc Jones
Add an additional Sandy(Ivy)bridge processor socket. Change-Id: I7eff7183d0c003e61fdda5350579f4d3dec7504d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12168 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-08cpu/amd/family_10h-family_15h: Increase BSP stack sizeTimothy Pearson
The additional local data storage requirements of the full DDR3 DRAM training algorithm make a BSP stack overrun a distint possibility. Increase the BSP stack size to compensate. Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11972 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-08cpu/amd/family_10h-family_15h: Add Family 15h microcode fileTimothy Pearson
Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11968 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-06amd/00730F01: Add correct CPU modelKyösti Mälkki
Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12284 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06AMD binaryPI: Fix include pathsKyösti Mälkki
Do not mix open-source AGESA and binaryPI includes. Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12283 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-05cpu/microcode: Remove EXTERNAL / ADDED_DURING_BUILD variablesTimothy Pearson
There has been a concerted effort to clean up coreboot's microcode handling that has included a move away from coreboot-specific microcode file collections. As a result, the ability to specify a single microcode file to be added to the image is of less utility than before. NOTE: This patch remove the built-in external microcode feature, however the user can still specify no microcode during build and manually add the correct microcode file(s) to the CBFS image after the build is complete. Change-Id: Ifea94c21e531a74953f5a0e2f489378c20ef3b5c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11903 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-03cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10hTimothy Pearson
The K8 PowerNow! state generator does not generate _PSS objects for nodes other than the first CPU package. This patch backports the PowerNow! core count fixes for Family 10h to the K8 CPUs. Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12286 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02cpu/amd/family_10h-family_15h: Use correct label for break stateTimothy Pearson
Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12101 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
Disable the parallel CPU initialization for model_206ax, that is Sandy Bridge and Ivy Bridge processors. We never did it the way that Intel recommends and it became unreliable with the introduction of SMM_MODULES in commit a3e41c0 Migrate 206ax to SMM_MODULES. Tested by booting kontron/ktqm77 2.6k times into Linux user space. No issues so far. Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-30cpu: port amd/pi to 64bitStefan Reinauer
Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11023 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-10-30smm: 64bit fixesStefan Reinauer
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11089 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstageTimothy Pearson
This mirrors a similar commit made to Family 10h support in changeset 11966 file model_10xxx_init.c TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222 Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12250 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30cpu/amd/model_fxx: Enable FIDVID code on Socket F K8Timothy Pearson
The existing Kconfig option for FIDVID was permanently set to "no" due to Kconfig stopping at the first matching value set when parsing the file. This patch moves the conditional set above the unconditional set, resolving the issue. Change-Id: Ic19f68f6b17943f9133ff32a9b6538f0bf942eca Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12224 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10hTimothy Pearson
Backport a handful of debugging routines and the extended APIC initialization code from Family 10h support to K8 support. Change-Id: I08cc5c8bc65635ce09a69e32940dd7edd8d3be87 TEST: Booted ASUS KFSN4-DRE with 1x Opteron 8222 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12251 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/car: Honor BKDG recommendations for DisFillP in CARTimothy Pearson
The recommendation to set DisFillP during CAR initialization on K8 NPT CPUs was ignored. The consequences of this are largely unknown; fix up coreboot to follow the recommendations. Change-Id: Ide512bbc1d9aa284179628e2aa598ef5475e8eeb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12249 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd/model_fxx: Fix invalid P-state power valuesTimothy Pearson
Change-Id: Ifdb1d1f267af289d962effe1150c7bc0a39cb5d2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12233 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30cpu/amd/model_fxx: Add Socket F CPU ID mappingsTimothy Pearson
Change-Id: If1df7f3ae9661fae49557c07def397b36b1d38f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12210 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEGPatrick Georgi
This mitigates the Memory Sinkhole issue (described on https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and crashing the system explicitly if LAPIC overlaps ASEG. This needs to happen without a data access (only code fetches) because data accesses could be tampered with. Don't try to recover because, if somebody tried to do shenanigans like these, we have to expect more. Sandybridge is safe because it does the same test in hardware, and crashes. Newer chipsets presumably do the same. This needs to be extended to deal with overlapping TSEG as well. Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11519 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-28cpu/intel/fsp_model_206ax: Load microcode in corebootMartin Roth
Intel's FSP 1.0 platforms are moving back to loading microcode in coreboot instead of in the FSP. Update the Ivy Bridge chips to be compatible. Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27cpu/amd/car: Add initial Suspend to RAM (S3) supportTimothy Pearson
Romstage handoff copied from cpu/intel/haswell/romstage.c Change-Id: I1e1a67fa3c2c13cebcf8f0af318055b9d97d0a59 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-09 21:40:56 +0000