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path: root/src/cpu
AgeCommit message (Expand)Author
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
2012-04-30Rework ACPI CST table generationStefan Reinauer
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
2012-04-26microcode: print date of microcode and unify outputStefan Reinauer
2012-04-26Revamp Intel microcode update codeStefan Reinauer
2012-04-25Replace cache control magic numbers with symbolsPatrick Georgi
2012-04-22amd: Fix unused variable warningVikram Narayanan
2012-04-20Revert wbind added to the reset_vectorMarc Jones
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12S3 code in vendorcode folder.zbao
2012-04-11Remove obsolete empy macro definitionRon Minnich
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
2012-04-05Invalidate cache before first jumpStefan Reinauer
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
2012-04-02S3 code whitespaces changes.zbao
2012-03-31Whitespace fixesPatrick Georgi
2012-03-31Intel cpus: get MAXPHYADDR at runtime for new CARKyösti Mälkki
2012-03-31Intel cpus: add hyper-threading CPU support to new CARKyösti Mälkki
2012-03-31Intel cpus: improve CPU compatibility of new CARKyösti Mälkki
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
2012-03-31Intel cpus: apply some good programming practices in new CARKyösti Mälkki
2012-03-31Intel cpus: cache actual size of the Flash ROM deviceKyösti Mälkki
2012-03-31Intel cpus: copy model_6ex CAR codeKyösti Mälkki
2012-03-30Make MTRR min hole alignment 64MBDuncan Laurie
2012-03-30Fix MB calculation in the reporting of the MTRR holeDuncan Laurie
2012-03-30MTRR: add alternate allocation method for odd memory mapsDuncan Laurie
2012-03-30Add Kconfig options to enable TSEG and set a sizeDuncan Laurie
2012-03-30drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not neededStefan Reinauer
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
2012-03-25Fix possible deadlock on SMP stop_this_cpuKyösti Mälkki
2012-03-25Intel cpus: Fix deadlock on hyper-threading initKyösti Mälkki
2012-03-17Intel cpus: Include CAR from socketKyösti Mälkki
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
2012-03-16ROMCC boards have no XIP limitPatrick Georgi
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
2012-03-16Fix address of IDT in real-mode entryKyösti Mälkki
2012-03-09move console includes to central console/console.hStefan Reinauer
2012-03-07Move C labels to start-of-linePatrick Georgi
2012-02-20Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.Marc Jones
2012-02-17Remove whitespace.Patrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh cpu wrapperKerry Sheh