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2019-08-22Add buffer_to/from_fifo32(_prefix) helpersJulius Werner
Many peripheral drivers across different SoCs regularly face the same task of piping a transfer buffer into (or reading it out of) a 32-bit FIFO register. Sometimes it's just one register, sometimes a whole array of registers. Sometimes you actually transfer 4 bytes per register read/write, sometimes only 2 (or even 1). Sometimes writes need to be prefixed with one or two command bytes which makes the actual payload buffer "misaligned" in relation to the FIFO and requires a bunch of tricky bit packing logic to get right. Most of the times transfer lengths are not guaranteed to be divisible by 4, which also requires a bunch of logic to treat the potential unaligned end of the transfer correctly. We have a dozen different implementations of this same pattern across coreboot. This patch introduces a new family of helper functions that aims to solve all these use cases once and for all (*fingers crossed*). Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-07device/pci: Rewrite PCI MMCONF with symbol referenceKyösti Mälkki
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-16device/pci_ops: Have only default PCI bus ops availableKyösti Mälkki
In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops. This change effectively inlines all PCI config accessors for ramstage as well. Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-03device/pci: Organize MakefileKyösti Mälkki
Use a single group for all CONFIG_PCI=y sources. Change-Id: I426f4398c01dfbf03b9dd2db8c7a964512c86d5e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31680 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11device/pci_early.c: Drop some guardsKyösti Mälkki
With PCI_DEV() always defined it is no longer necessary to exclude this code from building. Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-30device/pci_early: Fixes for __SIMPLE_DEVICE__Kyösti Mälkki
The feature is used to enable PCI MMIO accesses behind PCIe links (or bridges) before PCI enumeration has been completed. Add the feature for bootblock, verstage and postcar, it is required with add-on PCIe serial cards for early console output. It's up to the board specific code to configure PCIe root port prior to calling console_init() for this to work. Remove feature from ramstage, it bypasses any resource allocations and bus number assignments. For the moment PCI configuration support before ramstage is available only on ARCH_X86. Also switch from device_t to pci_devfn_t. Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-25device: Rename device_simple.c --> device_const.cNico Huber
In early stages (pre ramstage), we have two notions of devices. To access the hardware, "simple device" handles are used. These are plain numbers. To access the static information of the device tree, we use `struct device` pointers. This is referred to as DEVTREE_EARLY in the code. This file is about the latter and its name reflects that the tree remains unmodified. Change-Id: I31aeb118615e86026f7111f83a7866d4e7426170 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-24device: Always build device_simple.c for less code duplicationNico Huber
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-08Move `pci_ops_mmconf` from arch/x86/ to device/Nico Huber
MMConf is not architecture specific. We also always provide a pci_bus_default_ops() now if MMCONF_SUPPORT is selected. Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26062 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device: Include devicetree in SMM stageSubrata Banik
Allow bootblock to get access to the entire static device tree as other stages can access independently. TEST=SMM code now can access devicetree.cb variables. Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-18Reinvent I2C opsNico Huber
Do not use the global platform_i2c_transfer() function that can only be implemented by a single driver. Instead, make a `struct device` aware transfer() function the only interface function for I2C controller dri- vers to implement. To not force the slave device drivers to be implemented either above generic I2C or specialized SMBus operations, we support SMBus control- lers in the slave device interface too. We start with four simple slave functions: i2c_readb(), i2c_writeb(), i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec- tive SMBus functions. But we keep aliases because it would be weird to force e.g. an I2C EEPROM driver to call smbus_read_byte(). Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-25device: allow devicetree accesses in postcar stageAaron Durbin
Change-Id: Ib6f8ee937c4f3d8e2c0ff3851a819077fa499ccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27device: include devicetree in bootblock stageAaron Durbin
Allow bootblock to get access to the static device tree like other early stages. device_romstage.c was renamed to device_simple.c to better articulate the usage since it's not just being used in romstage. BUG=chrome-os-partner:55357 Change-Id: I3d63d2754c737cc738c09a3e3b3b468362fb78d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15837 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins)
2016-04-13device/pci_rom: Always use pci_romPatrick Rudolph
The following series always needs to access the functions provided pci_rom.c. Remove the dependency to CONFIG_VGA_ROM_RUN and depend on CONFIG_PCI instead. Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21device: Add i2c read/write register field APIYidi Lin
i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-22device: Use x86 specific code on x86-64Stefan Reinauer
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10584 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22device: Add class and subclass name supportLee Leahy
Add support to display class and subclass names for PCI devices. BRANCH=none BUG=None TEST=Build and run on strago/cyan. Change-Id: I5136fae45b8a1cd02541f233d29a246cdfcd8331 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c9b0d7201b09a06ea32f0db84187d15f767c80 Original-Change-Id: Ibf2ee89dd84040ca6ab0e52857a69f7ed0c28f37 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/9901 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Add software I2C supportJulius Werner
This patch adds the necessary platform glue to allow the use of software-driven I2C bit banging on the RK3288. This is just a debugging feature that can be used to reproduce certain I2C failure cases. Also fix Makefile verstage linking for the feature and add some new rk3288 IOMUX macros as needed. BRANCH=None BUG=None TEST=Added "CONFIG_SOFTWARE_I2C=y" to configs/config.veyron_jerry, wrapped Jerry's bootblock and verstage in software_i2c_attach/detach() calls, confirmed that both PMIC and TPM could be driven correctly with software I2C driver. Tried out different combinations of software_i2c_wedge_ack() and software_i2c_wedge_read() on the PMIC and observed transfer results with the hardware controller after reboot... the worst that would happen is that the first register read-modify-write (DCDC_ILMAX) would fail to read, but all later transfers would be fine. Since that register is written twice (due to current BUCK1 ramp implementation) and is not terribily important anyway, I think we don't need to worry about wedging problems. Change-Id: Iba801ee61d30fb1fd3aef8300612c67fa50c441b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24dfca9bab38a20c40ef0c2dd4c775b8d8f47487 Original-Change-Id: I96777300a57c85471bad20e23a455551e9970222 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247890 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-10PCI subsystem: Remove AGP bridge typeKyösti Mälkki
There is no auto-detection for AGP type and we have no hardware that selects this. Furthermore, we treat AGP bridges just like PCI bridges, there is no optimisation for higher bandwidth. Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8367 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-30i2c: Add software_i2c driver for I2C debugging and emulationJulius Werner
This patch adds I2C emulation in software through raw toggling of the SDA/SCL lines. Platforms need to provide bindings to toggle their respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs, currently only enabled for Tegra). This is mostly useful as a debugging feature, to drive unusual states on a bus and closely monitor the device output without the need of a bus analyzer. It provides a few functions to "wedge" an I2C bus by aborting a transaction at certain points, which can be used to test if a system can correctly recover from an ill-timed reboot. However, it can also dynamically replace the existing I2C transfer functions and drive some/all I2C transfers on the system, which might be useful if a driver for the actual I2C controller hardware is not (yet) available. Based on original code by Doug Anderson <dianders@chromium.org> and Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded controller project. BRANCH=None BUG=chrome-os-partner:28323 TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable() through the code and see that everything still works. Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198791 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682 Reviewed-on: http://review.coreboot.org/7947 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-13azalia: Shrink boilerplateVladimir Serbinenko
Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17device,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I73fe6f37c363f4bff332ca90178a236590067170 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6287 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-05gizmosphere/gizmo: Move support of SPD data in CBFSKyösti Mälkki
This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-09OxPCIe uart: Split PCI bridge controlKyösti Mälkki
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-12PCI: Add capability list parser to romstageKyösti Mälkki
These are almost one-to-one copies from pci_device.c. However, devicetree has not been enumerated yet and we have no console. Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-08-13Add a generic Intel HD audio (Azalia) module azalia_device.cAndrew Wu
This module uses cim_verb_data to detect and initialize HD audio codecs. The module source code is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3844 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>