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coreboot
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broadwell_refcode
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Some coreboot project code with my work
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dram
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Author
2015-06-23
ddr3: add missing newline
Patrick Rudolph
2015-06-23
ddr3: Fix SPD CRC calculation
Patrick Rudolph
2015-06-02
cbfs: new API and better program loading
Aaron Durbin
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-01
cbfs: correct types used for accessing files
Aaron Durbin
2015-01-12
src/device: Doxygen fixes
Martin Roth
2014-12-19
spd_cache debug: Log invalid CRC checksum
Tobias Diedrich
2014-12-07
ddr3: Plumber DIMM type to parsed structure.
Vladimir Serbinenko
2014-11-08
device/dram/ddr3.c: Fix sizeof on array func param overflow
Edward O'Callaghan
2014-07-29
sandy/ivybridge: Native raminit.
Vladimir Serbinenko
2014-07-05
gizmosphere/gizmo: Move support of SPD data in CBFS
Kyösti Mälkki
2013-12-17
device/dram/ddr3: Move CRC calculation in a separate function
Alexandru Gagniuc
2013-07-10
device: Fix spelling
Martin Roth
2013-06-04
DDR3: Add utilities for creating MRS commands
Alexandru Gagniuc
2013-06-03
dram: Add utilities for decoding DDR3 SPDs
Alexandru Gagniuc