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2019-10-24arch/acpi.h: Use of typedef for acpi_vfctHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I875ef2fa31e65750233fa8da2b76d8db5db44f2d Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-24arch/acpi.h: Use of typedef for acpi_vfct_image_hdrHimanshu Sahdev
Use of typedef and modify the usage accordingly. Change-Id: I65581702a60dbd286cb3910c6eeef5f9e1853cf1 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-18src: Remove unused include '<device/pci_ids.h>'Elyes HAOUAS
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device/root_device: Consolidate common _scan_bus() functionsNico Huber
scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device/dram/ddr4: Check spd_bytes_total and spd_bytes_used valuesElyes HAOUAS
The value stored to 'spd_bytes_total' is never read. Now it is fixed. This is spotted using clang-tool v9. Also add a check if spd_bytes_used and/or spd_bytes_total are reserved and make sure that spd_bytes_used is not greater than spd_bytes_total. Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-07src: Capitalize Super I/OElyes HAOUAS
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-07device: Rename scan_static_bus() -> enable_static_devices()Nico Huber
The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06device/pci: Enable full 16-bit VGA port i/o decodingNico Huber
So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in silent conflicts we preallocated resources. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As older systems seem rather safe and well tested, and newer systems should support this bit, we'll use it if possible and only warn if not. With old (AGP era) hardware one will likely encounter a warning like this: found VGA at PCI: 06:00.0 A bridge on the path doesn't support 16-bit VGA decoding! This is not generally fatal, but makes unnoticed resource conflicts more likely. Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35516 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04device/pci_device.c: Use verified boot to check opromFrans Hendriks
Before oprom is executed, no check is performed if rom passes verification. Add call to verified_boot_should_run_oprom() to verify the oprom. verified_boot_should_run_oprom() expects and rom address as input pointer. *rom is added as input parameter to should_run_oprom() which must be parsed to verified_boot_should_run_oprom().. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG1701 Change-Id: Iec5092e85d34940ea3a3bb1192ea49f3bc3e5b27 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-30device/pci_early: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. We have some use for PCI bridge configurations and resets in romstages, so expose them. Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30device/i2c_bus: Add i2c_dev_read_at16()Nico Huber
i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then reads bytes up to a given length into a buffer. Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30device,drivers/: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-27device: add commentary to dev_find_slot()Aaron Durbin
dev_find_slot() can sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22device/cardbus: Remove unnecessary bridge_ctrl bitmaskKyösti Mälkki
The bits PARITY and SERR are set unconditionally below. Change-Id: I03f53fe7f436f8feed7b34756439077f02a85565 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-09-22device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROLKyösti Mälkki
Read-modify-write needs to access the same register. Numerically both used defines are 0x3e, while register implementations are not identical but only similar. Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-09-22device/pci: Replace add with bitwise-orKyösti Mälkki
Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-17AUTHORS: Move src/device copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional cleanup - Unify "Inc" to "Inc." and "LLC." to "LLC" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie03a3ce1f6085494bd5f38da76e2467970cf301a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-15{cpu,device,drivers}: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15lib/coreboot_table: Show splashscreen in lb_table_initJohanna Schander
Every vga init implementation needs to cache the framebuffer state to be able to fill the lb_framebuffer struct later on in the fill_lb_framebuffer call. Showing the bootsplash afterwards guarantees to have the same interface into all the vga drivers. This is by far from ideal, as it only allows for a single driver at compile-time and should be adapted in the future. It was tested on the wip razer blade stealth using vgabios @ 1280x1024 and also in Qemu @ 1280x1024. By default the qemu framebuffer will be initialized in 800x600@32. This can be overwriten by configuration by setting CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES . Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-22Add buffer_to/from_fifo32(_prefix) helpersJulius Werner
Many peripheral drivers across different SoCs regularly face the same task of piping a transfer buffer into (or reading it out of) a 32-bit FIFO register. Sometimes it's just one register, sometimes a whole array of registers. Sometimes you actually transfer 4 bytes per register read/write, sometimes only 2 (or even 1). Sometimes writes need to be prefixed with one or two command bytes which makes the actual payload buffer "misaligned" in relation to the FIFO and requires a bunch of tricky bit packing logic to get right. Most of the times transfer lengths are not guaranteed to be divisible by 4, which also requires a bunch of logic to treat the potential unaligned end of the transfer correctly. We have a dozen different implementations of this same pattern across coreboot. This patch introduces a new family of helper functions that aims to solve all these use cases once and for all (*fingers crossed*). Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20device/oprom: Drop unnecessary AMD headersKyösti Mälkki
Change-Id: I548dfa053f195b1ea87568240bf0041bb193d825 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-14dram: Add basic DDR4 SPD parsingAndrey Petrov
Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table 17. XMP, schemas, extended field parising is totally not yet implemented. Also, put CRC function used in DDR2, DDR3 and DDR4 ina common file. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-02device/pci_ops: Make PCI_BDF() available in all stagesKyösti Mälkki
Caller needs to take into account that bus numbers may have not been assigned yet. Same issue existed before with early ramstage and mostly does not cause problems when used with static devices on bus 0. Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34614 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31device: Constify `dev` argument to (probe|find)_resource()Nico Huber
Change-Id: I7abca61db61d2f2df149ca601631c45d8c4f342e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34613 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26src/device/oprom: Fix bootsplash display code for optionromsJohanna Schander
So far the bootsplash is only correctly rendered if the framebuffer is set up as 1024x768@16. Different resolutions did not show anything, differnent depth resulted in the distorted images. This commit removes this limit by using the actual framebuffer resolutions and combines the code for x86 and yabel. For the moment the bootsplash is still limited to VGA-OptionROM framebuffer init. It was tested in 1280x1024@32 on the wip razer blade stealth using the intel vgabios. Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26oprom/yabel: Fix comment to fix the buildKyösti Mälkki
Old comment did not match the pattern required to not flag the fall-through as an error. Change-Id: I2afaca969c295a5dc4389dad0ce898c87bb841a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Johanna Schander <coreboot@mimoja.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-24device: Default to VESA/linear framebuffer for ChromeOSNico Huber
Building for ChromeOS implies the use of Depthcharge which doesn't support legacy text mode. Change-Id: I7fd82bfed1e59de2de75419cfaea6f0c19cfdf5e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34483 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19device/device_util.c: Correct format specifierJacob Garber
path.mmio.addr is a uintptr_t, which is an unsigned long. Change-Id: I5e43e0ab65cf59819abe1dde43143ff98e4553b0 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19device/oprom: List all supported vesa mode by opromSubrata Banik
This patch lists all supported vesa mode by oprom using Function 0x4F00 (return vbe controller information). This information might be useful for user to select correct vesa mode for oprom. TEST=Enabling external pcie based graphics card on ICLRVP Case 1: with unsupported vesa mode 0x118 Now coreboot will show below msg to user to know there is a potential issue with choosen vesa mode and better users know the failure rather going to depthcharge and debug further. Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4118 VBE: Function call invalid with unsupported video mode 0x118! User to select mode from below list - Supported Video Mode list for OpRom are: 0x110 0x111 0x113 0x114 0x116 0x117 0x119 0x11a 0x165 0x166 0x121 0x122 0x123 0x124 0x145 0x146 0x175 0x176 0x1d2 0x1d4 Error: In vbe_get_mode_info function Case 2: with supported vesa mode 0x116 Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 4116 VBE: resolution: 1024x768@16 VBE: framebuffer: a0000000 VBE: Setting VESA mode 4116 VGA Option ROM was run Change-Id: I02cba44374bc50ec3ec2819c97b6f5027c58387f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34284 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19device/pci_rom.c: Fix out of bounds readJacob Garber
run_rom->data is a uint16_t, so use the appropriate read function. Change-Id: Icc14421412885495df90c90ed7da6e7d2eba4182 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402145 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34372 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18device/oprom/realmode: Add vbe return status support as per VBE spec 3.0Subrata Banik
Existing coreboot oprom implementation relies on user selected vesa mode through CONFIG_FRAMEBUFFER_VESA_MODE Kconfig option and expects that all oprom might support user selected vesa mode. Take an example: Enabling AMD external radeon PCIE graphics card on ICLRVP with default vesa mode 0x118. Unable to get valid X and Y resolution after executing vbe_get_mode_info() with 0x4118, return data buffer shows 0x0 resolution. It causes further hang while trying to draw bmpblk image at depthcharge. This patch checks for output register AH in all vbe function (0x3 and 0x4f00/1/2) and die() if returns error. Change-Id: Iacd2ce468e038a14424f029df3a0adec3e5fa15c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-18devicetree: Add accessors for chip_infoKyösti Mälkki
Apply uniform style of error messages for missing device nodes and chip_info. Change-Id: I70def4599509b8193e44ea3f02c4906f865b4469 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-17soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki
Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15device: Remove device->ops from early stagesKyösti Mälkki
Change-Id: I7a361187570716df94a3fd441ae78c0f805b1dda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33921 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13device/hypertransport.c: Remove dead assignmentJacob Garber
last_unitid is immediately overwritten in the do loop, so this assignment is not needed. This a relic from old code that commit 13f1c2af8b made obsolete, but was never removed. Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-13device/device_util: Fix encoding the USB device pathKarthikeyan Ramasubramanian
USB device id does not get included because of the logical OR operation. Fix encoding the USB device path. BUG=None BRANCH=None TEST=Boot to ChromeOS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I79317da6d9c7cd177bd7bbbba1f1ccebe076930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34245 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12device/oprom: Replace uses of dev_find_slot()Kyösti Mälkki
The call to dev_find_slot() may return PCI devices that are disabled or unaccessible, as PCI enumeration does not remove nodes from all_devices linked list. Use PCI topology search instead. Change-Id: I00233177e5572ca79002a7d141cda1b94b966330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34083 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12device/pci: Declare pcidev_path_on_bus()Kyösti Mälkki
It is recommended to never reference PCI busses using a static number. There is exception with OPROM execution, where we want to translate the bus number captured from the actual IO operation into a matching device node in the devicetree. Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12device/pci: Replace use of dev_find_slot() for IRQsKyösti Mälkki
Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10device/oprom: Replace CONFIG() preprocessor statementsKyösti Mälkki
Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-10device/oprom: Reduce indentationKyösti Mälkki
Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-07device/pci: Declare pci_root_bus()Kyösti Mälkki
This is used a lot, cache the result so search of domain from devicetree is only done once. Improvement only applies when MAYBE_STATIC evaluates to static. Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-05device/pci_rom.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: Ie9adb60323742d379cc4ad0af069a793b9ddd79b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33330 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-04device/pci_ops: Define pci_find_capability() just onceKyösti Mälkki
Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02device/pci_rom: Fix redundant pci_rom_probe() callsKyösti Mälkki
For the PCI_VENDOR_ID_ATI case, we can rely on pci_rom_acpi_fill_vfct() to make the call if necessary. For hardware other than ATI, pci_rom_probe() was already called from pci_rom_ssdt() and pci_dev_init(), so PCI_ROM_ADDRESS BAR is already enabled, if requested so. Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02device/pci_rom: Fix on-board optionrom addressKyösti Mälkki
The function pci_rom_probe() may be called multiple times for a device. For cases where CBFS does not contain optionrom file, only the first time probing for the on-board ROM chip worked. PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all the reserved bits of PCI_ROM_ADDRESS register to get correct physical address for rom_header. Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 01:03:45 +0000