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2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-13payloads: add iPXE 'payload' buildMartin Roth
We already have the ability to add a pxe rom to cbfs, but it needs to be configured and built separately. This moves the existing Kconfig options for PXE from device/Kconfig and the top level Makefile.inc to payloads, and adds the option to download and build iPXE as part of the coreboot build process. This configures the serial output of iPXE to match coreboot's serial port configuration by editing the .h files. iPXE doesn't give any real build-time method of setting these configuration options. Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14085 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13src/device: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14325 Reviewed-by: Myles Watson <mylesgw@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13device/pci_rom: Always use pci_romPatrick Rudolph
The following series always needs to access the functions provided pci_rom.c. Remove the dependency to CONFIG_VGA_ROM_RUN and depend on CONFIG_PCI instead. Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21device: Add i2c read/write register field APIYidi Lin
i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21device/dram/ddr3: fix debug outputPatrick Rudolph
Add missing punctuation and align output. No functionality is changed. Old logging output: Revision: 11 Type : b Key : 2 Banks : 8 Capacity: 4 Gb Supported voltages: 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes DIMM Rank1 Address bits mirrored!!! DIMM Reference card B DIMM Manufacturer ID cd04 DIMM Part number F3-1866C9-8GSR XMP Profile 1 Max DIMMs per channel: 4 XMP Revision: 1.3 Requested voltage: 1500 mV New logging output: Revision : 11 Type : b Key : 2 Banks : 8 Capacity : 4 Gb Supported voltages : 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes Rank1 Address bits : mirrored DIMM Reference card: B Manufacturer ID : cd04 Part number : F3-1866C9-8GSR XMP Profile : 1 Max DIMMs/channel : 4 XMP Revision : 1.3 Requested voltage : 1500 mV Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14083 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05Kconfig: hide useless options on ARM.Vladimir Serbinenko
Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03src/device/dram/ddr3: Parse additional informationPatrick Rudolph
Parse manufacturer id and ASCII serial. Required for SMBIOS type 17 field. Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13862 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
Some vendors store lower frequency profiles in the regular SPD, if the SPD contains a XMP profile. To make use of the board's and DIMM's maximum supported DRAM frequency, try to parse the XMP profile and use it instead. Validate the XMP profile to make sure that the installed DIMM count per channel is supported and the requested voltage is supported. To reduce complexity only XMP Profile 1 is read. Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the default SPD. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13486 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-18device: Add device path display supportLee Leahy
Add an optional routine to translate the device path types into a string for display. TEST=Build and run on Galileo Change-Id: Iea5d0a2430d9a8546105324e2beda0955210dca9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16device/pci_rom: Rename missleading ON_DEVICE_ROM_RUNPatrick Rudolph
The Kconfig option "ON_DEVICE_ROM_RUN" suggests that PCI Option ROMs are run, but in fact it only controls the loading of PCI based Option ROMs. At the moment coreboot only executes Option ROMs if they are VGA Options ROMs and the VGA Option ROM execution flag is enabled. Setting ON_DEVICE_ROM_RUN with VGA Option ROM execution disabled has no effect. Clarify that this flag controls the loading behaviour and not the execution behaviour. Change-Id: Ie3e503cb145f9b7ce613755e60ac0f6c00f2bcdb Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26arch/x86: Drop arch/pciconf.hStefan Reinauer
It's unused, so get rid of it. Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13177 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18device/oprom/yabel: Update BSD license headersMartin Roth
All of the yabel files are BSD licensed. Change-Id: Ibe0b3bb67a96c57b5d693676f5e8f19b6bed90fa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12972 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-29device/pnp: Ability to set vendor specific logical device configDamien Zammit
According to the PNP ISA v1.0a spec, config registers in the range of 0xf0 up to 0xfe are vendor defined and may be used for any purpose. Config register 0xff is reserved and is defined as such. Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa are able to be set using the PNP_MSCx bit flag masks. This patch adds support for all 15 vendor specific config registers, and updates the existing superio pnp_info to use them where appropriate. Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20x86emu: Remove XFree86 CVS tagsStefan Reinauer
They're not supported by git. Change-Id: I8157cdc0f5f4072af588772680741b72d21a9223 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12494 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20x86emu: Undefine _NO_INLINEStefan Reinauer
Never defined by the server. Change-Id: If22727cf3953c2931d107146fb99b5997f8a13d5 Original-Reviewed-by: Eric Anholt <eric@anholt.net> Original-Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12493 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20x86emu: Fix some set-but-not-used warnings.Stefan Reinauer
Change-Id: Ide861733d721a21b77862076bf7ad70c7ee6a472 Original-Reviewed-by: Adam Jackson <ajax@redhat.com> Original-Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-19device/device.c: remove warning for missing apic read resourcesMartin Roth
We have had the "APIC: 00 missing read_resources" messages for many years. It's obviously not an error, and also doesn't cause boot failures. Therefore, remove the message. Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Revert "device/pciexp_device: Tune PCIe bridges before scanning children"Kyösti Mälkki
This reverts commit 785b3eb6e8fcafb38395eec00f4f0fc0e906c7cc. The commit re-tuned the upstream link again, it does not tune secondary side. Change-Id: I9be70e95b06ceff99beba8a7c7eb6402b32fcca1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12253 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-27device: Stop and output time in `scan_bus()`Paul Menzel
Output how long it took to scan a bus. Note, that the function `scan_bus()` is called recursively. Change-Id: I6335e10db783f092ea18d3a1c79f93135bee5826 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12103 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-25yabel: explicitly cast values to match printk expectationsStefan Reinauer
Change-Id: Id2230ecd800b138b6ccbbac318e71c9edf076c75 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12116 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25yabel: Use IS_ENABLED where appropriateStefan Reinauer
Change-Id: Ib078b21ddf0493ad6795c6ab79125b3917ff7049 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12115 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25yabel: Don't cast pointer to u32Stefan Reinauer
Change-Id: I45b3412263507d92f443743d2ee63c9a8ef94795 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12114 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25Separate bootsplash image menuconfig option from othersKonstantin Aladyshev
The possibility of adding a bootsplash image to ROM should be independent from VGA_ROM_RUN and VESA menuconfig options. For example, the stored image could be saved in CBFS not for coreboot but for later use in SeaBIOS. Change-Id: I3a0ed53489c40d4d44bd4ebc358ae6667e6c797f Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/12129 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25device/pciexp_device: Tune PCIe bridges before scanning childrenTimothy Pearson
Change-Id: Ieccafe8864d622c651e6a524e9898505ded15e54 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12187 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25device/pci_device: Set bridge primary bus number before scanningTimothy Pearson
Certain devices, such as the Intel 82575GB, contain multiple nested PCIe bridges (for example the PES12N3A). Coreboot does not set the primary bus number of the lower bridges, causing upstream forwarding failure. This in turn causes coreboot to fail to find the lowest devices (in this case the NICs), and as a result the required resources are not allocated and the NICs do not function. Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12186 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24southbridge/amd/sb700: Allow use of auxiliary SMBUS controllerTimothy Pearson
Change-Id: I29ece10eeefc2c75a3829c169f1e1aede7194ec2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12079 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2015-10-24device/smbus: Avoid infinite loop if SMBUS device has wrong parentTimothy Pearson
If an SMBUS device in devicetree.cb is placed under a parent device that does not have an SMBUS controller, coreboot will enter an infinite loop and hang without printing any failure messages. Modify the loop to exit under these conditions, allowing the failure message to be printed. Change-Id: I4c615f3c5b3908178b8223cb6620c393bbfb4e7f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12131 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins)
2015-10-23device/hypertransport: Add additional debug outputTimothy Pearson
Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11945 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-10-22allocator: Page align memory mapped PCI resourcesNico Huber
To help hypervisors to assign PCI devices individually to virtualization guests, page align dynamically allocated MMIO resources. Tested with kontron/ktqm77 which has dynamically configured onboard devices on the root bus and secondary buses. Booted Linux and checked the configuration with `lspci -v`. Got the configuration through Muen's tools which are very picky about overlapping and alignment. Booted a Muen based system that uses many onboard devices. GMA, xHCI and one NIC (on a secondary bus) were verified to function properly. Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12111 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11realmode/x86: Export vbe_mode_info_valid also in text mode.Vladimir Serbinenko
Fixes linking error. Specifies that we're in text mode. Change-Id: I7ad258961039c19e1491e2b3832b003671d8a5c7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11848 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-09-05symbols: add '_' to pci_drivers and cpu_drivers symbolsAaron Durbin
In order to prepare for more unification of the linker scripts prefix pci_drivers, epci_drivers, cpu_drivers, and ecpu_drivers with an underscore. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built different boards includes ones w/ and w/o relocatable ramstage. Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11506 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-30Kconfig: Remove EXPERT modeAlexandru Gagniuc
After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-08-30Kconfig: Don't 'select' options based on PAYLOAD_SEABIOSAlexandru Gagniuc
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11293 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2015-07-16x86 realmode: Set up the 8254 timer before running option romzbao
If the 8254 is not set up, the external graphics option rom hangs and never returns. The code is tested on AMD/bettong. Change-Id: I0022de9d9a275a7d4b7a331ae7fcf793b9f4c5f5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/10903 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-12x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVELMartin Roth
This protection didn't make sense to me - it seems like things would probably break if printf wasn't defined anyway. Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09device: remove unused x86 include from common codeStefan Reinauer
The include breaks compilation on ARM with clang. Change-Id: I1ce0d58dbcbb8785c23739670c8c9574c329a81c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10858 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-23ddr3: add missing newlinePatrick Rudolph
Add missing newline to SPD CRC verification error message. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Id1a0a2329507975c3f66ab884f6e26d99003318e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10636 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23ddr3: Fix SPD CRC calculationPatrick Rudolph
Use the correct SPD size for crc calculation. sizeof(*spd) returns 4 while sizeof(spd_raw_data) returns the expected value of 256. Fixes erroneous printing of "ERROR: SPD CRC failed!!!" in raminit log. Verified by testing this code on Intel IvyBridge and Gigabyte GA-B75M-D3H. Change-Id: Iba305c69debd64fa921e08e00ec0a3531c80f56f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10629 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-22oprom: Fix for 64bitStefan Reinauer
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10591 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22device: Use x86 specific code on x86-64Stefan Reinauer
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10584 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-17PCIe : Adding some error/not-null condition checkingPratik Prajapati
This patch checks for following conditions (1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found then don't enable LTR. (2) 2.1) set_L1_ss_latency is member if ops_pci, which could be NULL. so confirm ops_pci is not NULL before calling its member function. 2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency. BUG=none BRANCH=none TEST=build and boot coreboot with L1 substate enabled on sklrvp3. Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181 Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-13Move remap_bsp_lapic to AMD specific codeStefan Reinauer
It's not used outside of very old AMD CPUs. Change-Id: Ide51ef1a526df50d88bf229432d7d36bc777f9eb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10538 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-10resource: Refactor IORESOURCE flags useKyösti Mälkki
The type of a resource is really an enumeration but our implementation is as a bitmask. Compare all relevant bits and remove the shadowed declarations of IORESOURCE bits. Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8891 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10PCI subsystem: Drop PCI_64BIT_PREF_MEM optionKyösti Mälkki
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 15:20:01 +0000