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2018-06-04device: Only expose VGA_ROM_RUN on supported architecturesPatrick Rudolph
The yabel emulator depends on IO ports, that aren't available on ARM and MIPS. Add additional dependencies to fix compilation errors with the default configuration. Change-Id: If0e28b356c01cb3ae0739a54aa3531a2acedbfbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26754 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25device: Move find_dev_path() to device_const.cKyösti Mälkki
Change-Id: I8a27aa7157b5706623272ba9354ed8dff9b8184f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25device: Move dev_find_path() to device_const.cNico Huber
Make it available early and use it in dev_find_next_pci_device(). Change-Id: I1d0ad07f37ea79dae2b9a592fcccba5e03fd86d5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-25device: Rename device_simple.c --> device_const.cNico Huber
In early stages (pre ramstage), we have two notions of devices. To access the hardware, "simple device" handles are used. These are plain numbers. To access the static information of the device tree, we use `struct device` pointers. This is referred to as DEVTREE_EARLY in the code. This file is about the latter and its name reflects that the tree remains unmodified. Change-Id: I31aeb118615e86026f7111f83a7866d4e7426170 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-24device: Always build device_simple.c for less code duplicationNico Huber
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22src/device: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. The function prototype for "struct device *add_cpu_device" is already correct and doesn't need to be fixed. Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22device/device_util.c: Remove space after sizeofElyes HAOUAS
Change-Id: Ic8b77c78739badbea398053944484a55f715d03d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11devicetree: Add USB device typeDuncan Laurie
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08Move `pci_ops_mmconf` from arch/x86/ to device/Nico Huber
MMConf is not architecture specific. We also always provide a pci_bus_default_ops() now if MMCONF_SUPPORT is selected. Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26062 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08device/pci_ops: Remove unnecessary weak implementationNico Huber
I doubt this is or will ever be referenced anywhere. And if, we probably shouldn't return. Change-Id: I3704fec694c5e5a9d5ff7d78d8bf2f23cf463e3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04device/root_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pci_class.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pcix_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/smbus_ops.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/cardbus_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pciexp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pnp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02src/device: Fix discarded-qualifiers compilation issueSubrata Banik
coreboot build is broken due to CL: I6830a65bc9cea2907f4209bb97a53ccebcbf248d This patch ensures to build coreboot successfully. Change-Id: I4c9dfc9b19ce159ce1abcfbb287be4ce273cbaf1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02pci: Fix MMCONF_SUPPORT on non x86Patrick Rudolph
Move x86 specific pci_bus_default_ops into arch/x86 folder. Fixes compilation on platforms that do neither have MMCONF_SUPPORT nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI. Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02software_i2c: Improve error behaviorJulius Werner
This patch fixes a bug in the software_i2c (bitbang) framework where it would previously not return an error when receiving a NACK on a write transaction (deviating behavior from our hardware I2C drivers). It also adds explicit error codes to be returned for the different kinds of failure conditions so they are more useful for debugging when dumped. Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-04-30device: constify some variablesLubomir Rintel
Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26device: Add flag to disable PCIe ASPMNico Huber
For broken devices that spuriously advertise ASPM, make it possible to decide ASPM activation in the device driver. Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25617 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23device/oprom/yabel: Fix spelling of *successful*Paul Menzel
Remove one *l* at the end. Change-Id: Ife5af64b380dc5d31f22873f1639382d2bf9a5d9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20device/oprom/yabel: Fix vbe-buffer index in vbe.cHal Tsai
There's a issue about {VbeSignature to "VBE2" to indicate VBE 2.0+ request}, these indexes are counted wrong. Change-Id: I8ec85df60076162518aa55a94fa7b66c0c2391ab Signed-off-by: Hal Tsai <hal_tsai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-16device/dram/ddr3: improve XMP supportDan Elkouby
- Fix offsets for supported CAS latencies - Add support for reading CWL and CMD rate from the profile Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-09device/dram/ddr2.c: Add methods to compute to identify dramArthur Heymans
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till 98. Compute a crc16 over that data to provide a solid way to check DIMM identify. Reuse the crc16 function from ddr3.c to do this. Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-03-14src/device/dram/ddr2: Fix supported burst lengthsElyes HAOUAS
Supported burst lengths are described at byte 16 Change-Id: I502710bdac7eec715b29febefd64be88e5a1b80a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-08timestamps: Add timestamps around the vbios load & initMartin Roth
Add timestamps before and after the vBIOS load and after the vBIOS run. This lets us see exactly how long it took to load it from the ROM chip, and how long it takes to run. BUG=b:64549506 TEST=Build & boot Grunt, see vBIOS load & initialization times. Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
In order for ddr2.h and ddr3.h to be included in the same file it cannot have conflicting definitions, therefore rename a few things and move some things to a common header. Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-02-22device: Include devicetree in SMM stageSubrata Banik
Allow bootblock to get access to the entire static device tree as other stages can access independently. TEST=SMM code now can access devicetree.cb variables. Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01Add a default path for vbt.binArthur Heymans
FSP_GOP needs a vbt.bin to work but before this patch it was able to build with the default configuration which was an empty path for vbt.bin. To make Jenkins happy don't select FSP_GOP by default, at least until all boards have the proper vbt blobs in the blobs repo. Change-Id: Ibc36d6d4dd1a56c53819b169e6f4799ce3c23e03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-01device: add ALWAYS_RUN_OPROM optionAaron Durbin
Certain platforms require that the option rom always needs to be ran in order for display to work correctly. Therefore, provide this ability for the platform to select such that we force option rom loading. BUG=b:72400950 Change-Id: I597bc8af7ac8b68fe8505aac5f1c7e1ccd34ac27 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23505 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01device/pci_device: remove #if/#endif in oprom logicAaron Durbin
Use C if conditions instead of preprocessor macros. BUG=b:72400950 Change-Id: I8107f94b9ecb6f32c569cad0bcb3d51ab39aa35c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23504 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31device/pci_rom: Write _ROM method for VGA devicesPatrick Rudolph
Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24device/i2c_bus: allow i2c_bus and i2c_simple to coexistAaron Durbin
If one wants to implement both i2c_bus.h and i2c_simple.h APIs the compilation unit needs to be guarded or coordinated carefully with different compilation units. Instead, name the i2c_bus functions with _dev such that it indicates that they operate on struct device. One other change to allow i2c_bus.h to be built in non-ramstage environments is to ensure DEVTREE_CONST is used for the dev field in struct bus. BUG=b:72121803 Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-20device/dram/ddr2.c: Store the checksum in the decoded SPD structArthur Heymans
Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-13device: Make pci_dev_ops_pci structure globalSubrata Banik
This patch makes pci_dev_ops_pci structure global so that caller can make use of this structure using extern. Change-Id: I8de919aacccbc062475fb04f59ffb4957d3460b9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-08device/pciexp_device: Set values numerically instead of as bitmaskPatrick Georgi
As noted on linux-pci, we have a weird way to handling "value" and "scale" fields that are supposed to contain numerical values: we encode them as a bitfield. Instead define the two fields (offset and mask) and use numbers. Another issue, not fixed in this CL, is that we write hard-coded values while these fields really need to contain the max() of acceptable delays of the downstream devices. That way the controller can decide whether or not to enter a deeper power management state. It's noted as a TODO. Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-on: https://review.coreboot.org/22740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-15device: further untangle device_t from struct deviceAaron Durbin
This further allows compilation units to be re-used without having to add macro guards because of declarations not being around in the __SIMPLE_DEVICE__ case. These declarations are for functions that operate on struct device. struct device is a known type so just expose the functions using the correct type. Also, DEVTREE_CONST is empty while in ramstage so there's no reason to separate the declarations. Lastly, fix up device_util.c to use the proper types. It's only compiled in ramstage and it only operates on struct device. Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07device/device_util: Add string for DEVICE_PATH_NONEPatrick Rudolph
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE can be translated to string and shouldn't be translated by "Unknown device path type: 0". Makes console output a lot prettier and readable. Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots. Change-Id: I08d471d8217f966e80daefe2d9971e357defde62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13src/device: Update LTR configuration schemeAamir Bohra
This patch moves out LTR programming under L1 substate to pchexp_tune_device function, as substate programming and LTR programming are independent. LTR programming scheme is updated to scan through entire tree and enable LTR mechanism on pci device if LTR mechanism is supported by device. BRANCH=none BUG=b:66722364 TEST=Verify LTR is configured for end point devices and max snoop latency gets configured. Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/21868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26device/dram/ddr2.c: fix a hidden syntax error introduced earlierBill XIE
A regression is hidden in commit 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 (device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag ), which breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set. Maybe it had better implement "printram" and the like as inline functions instead of macros. Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21673 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flagArthur Heymans
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note 4 says bit7 of byte 12 indicates whether the assembly supports self refresh. This patch decodes this and modifies decoding tRR accordingly. Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-22device/dram/ddr2: Add break to several case statements that lack itPatrick Georgi
For all valid SPD values the same decoded tRR was returned. Change-Id: Iec43f8c7460dfcf68f7c92dfdf333b004f368b65 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Coverity Scan #1381369, #1381370, 1381371, 1381372, 1381373 Reviewed-on: https://review.coreboot.org/21642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
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