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2021-05-11device/device.c: Print bus numbers in decimalAngel Pons
For consistency with other log messages, print bus numbers in decimal. Change-Id: Ib08ae40fc67c5f8fafd760e8dbb729d6de34c2bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-10device: Drop unused `uma_memory_{base,size}` globalsAngel Pons
These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-19device/azalia_device.c: Add option to lock down GCAPAngel Pons
On Intel 6-series PCHs, the GCAP register is R/WO (Read / Write Once), and needs to be written to after the HD Audio controller is taken out of reset. Add a Kconfig option to read and write back GCAP in order to lock it down. Follow-up commits will select this option when switching platforms to use common Azalia code, to preserve original behaviour. Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-18device/Kconfig: Adapt PCIEXP_HOTPLUG_BUSESNico Huber
The default of 32 buses per hotplug bridge is rather high. Especially for platforms that limit MMConf space to 64 buses: they run out of numbers if there is more than a single hotplug bridge. Lower the default to * 8 if MMConf is limited to 64 or less buses, * 16 if MMConf is limited to 128 or less buses. Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52069 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14Rename do_printk() to printk()Nico Huber
The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06device/i2c_bus.c: Correct code styleFrans Hendriks
device: Correct code style Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition. - Remove unnecessary newlines. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-05device/dram/ddr3: Drop unused MRS helpersAngel Pons
These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05device/dram/ddr4.h: Align with DDR3 and DDR2Angel Pons
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons
To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Get rid of useless typedefsAngel Pons
These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24device/azalia_device.c: Program beep verbsPatrick Rudolph
Change-Id: I11b362d5e586194501de5dbd11f9c934a9d53940 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24device/azalia_device.c: Introduce AZALIA_MAX_CODECSAngel Pons
Add the AZALIA_MAX_CODECS Kconfig option and use it. Change-Id: Ibb10c2f2992257bc261e6cb35f11cc4b2d956054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-03-24device/azalia_device.c: Correct STATESTS access widthAngel Pons
The HD Audio spec states that the STATESTS register is 16 bits wide. Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24device/azalia_device.c: Unify `wait_for_valid` timeoutsAngel Pons
The timeout is never reached when the codec is functioning properly. Using a small timeout value can result in spurious errors with some codecs, e.g. a codec that is slow to respond but operates correctly. When a codec is non-operative, the timeout is only reached once per verb table, thus the impact on booting time is relatively small. So, use a reasonably long enough timeout to cover all possible cases. Remove the unconditional 25 µs delay and increase the timeout delay. The new value of 1 ms is the maximum of all existing implementations. Currently, the only boards using this code are AMD reference boards: - AMD Bilby - AMD Mandolin - AMD Padmelon Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-22device/azalia_device.c: Switch to stopwatchPatrick Rudolph
Use timer.h helpers instead of open-coding timeout handling in polling loops. The 25-microsecond delay in `wait_for_valid` looks odd, and may be removed in subsequent commits. For now, preserve existing behavior. Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50789 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15pciexp_device: Rewrite LTR configurationNico Huber
I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14device/pciexp_device.c: Remove CPP guardingArthur Heymans
Let the linker do its job. This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms. Change-Id: I46560722dcb5f1d902709e40b714ef092515b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-13soc/amd/common/block/graphics/graphics: GOP: load VBIOSNikolai Vyssotski
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000) since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not set). Add Cezanne GFX PID. BUG=b:171234996 BRANCH=Zork Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-12pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 properNico Huber
Replace the existing, odd looking, unordered definitions used for LTR configuration with the usual names used by upstream libpci. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Fixes: Code looked like UEFI copy-pasta. Header file was a mess. Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24device/device.c: Rename .disable to .vga_disableArthur Heymans
This makes it clear what this function pointer is used for. Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph
Move SPD manufacturer ID decoding to device/dram. Will be used by the following patch outside of SMBIOS scope as well. Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`Paul Menzel
It’s good practice to put the unit into the name. Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-15src/device: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I30ed9661d8e84be49d362baafbb2bc624952c287 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50522 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10device/azalia_device: Add mainboard hook to program codecsAngel Pons
On some mainboards, codec configuration depends on settings that are only known at runtime, which is impossible to specify using one verb table. Add an optional `mainboard_azalia_program_runtime_verbs` hook where mainboards can program runtime-dependent codec verbs. Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device: Add function to program a verb tableAngel Pons
On some boards, Azalia configuration depends on config settings that are not known at compile-time. Expose a function to program a verb table, to be used in subsequent commits. Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device.c: Correct print formatAngel Pons
The type of `verb_size` is unsigned, thus use `%u` to print its value. Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-06soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAYKyösti Mälkki
It was commented that the need for the delay was mainly related to external displays and only with VBIOS execution. Move the delay such that it is done only when we actually need to execute the VBIOS aka option rom. A delay is currently only defined for librem/purism_bdw in its Kconfig. As the description of the issue sounds like it would equally happen on other platforms when VBIOS is involved, promote the Kconfig visible option to global scope. Change-Id: I4503158576f35057373f003586bbf76af4d59b3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05device/device.c: Print done at end of assign_resources()Frans Hendriks
First and last printk() log the same string. Add done at end of function. BUG = N/A TEST = Build and boot faceboot FBG1701 Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05device: correct code styleFrans Hendriks
Revise the following aspects to follow coreboot's coding style: - Drop braces for single-statement condition and loop bodies. - Use `__func__` to print the current function's name. - Reflow pointer dereferences to fit in a single line. - Adjust the `*` position in pointer variable declarations. - Drop unnecessary `else` statements. BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01device/oprom/include/x86emu/fpu_regs.h: Fix lint errorFrans Hendriks
`make lint` reports errors and warnings Solve the next errors: - SPACE_BEFORE_TAB - SPACING BUG = N/A TEST = Build Compulab Intense-PC with secure oprom enabled Change-Id: Ic7062e07a76bf95fe8e2e849f1d14342c9081a23 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49938 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30device: Drop `mmconf_resource_init` functionAngel Pons
All uses of `mmconf_resource_init` have been replaced in previous patches with `mmconf_resource`, which uses Kconfig symbol values. Change-Id: I4473268016ed511aa5c4930a71977e722e34162a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30device/Kconfig: Introduce MMCONF_LENGTHAngel Pons
This is necessary because ASL Memory32Fixed values cannot contain operations, even if they can be evaluated to constants. Add a sanity check in pci_mmio_cfg.h to ensure consistency with MMCONF_BUS_NUMBER. Change-Id: I8f0b5edf166580cc12c1363d8d6b6ef0f2854be9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50033 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27src/device: Don't die() on vBIOS errorsMartin Roth
Systems can boot to the OS without a display. Don't kill the boot process based on a vBIOS error, instead just display a warning. If the issue is actually fatal for some reason, it's going to die at some point anyway. BUG=b:175843172 TEST=Boot morphius to OS without a display BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7d261321cdbe423dd754f6a354e5f50b53563fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-26device/pci_device.c: Use __func__Elyes HAOUAS
Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24device/pci_rom.c: Use __func__Elyes HAOUAS
Change-Id: I24c40d511eeaa5073acd2b47b20b4ec2f85bb69e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-18device/oprom/x86emu/sys.c: Use __func__Elyes HAOUAS
Change-Id: Ia278e1f2d1162fa9541bf0cead3b2734144190be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18device/xhci.c: Remove repeated wordElyes HAOUAS
Change-Id: Ia1648bd7ba4858268ca5f1a5c7b42b7de717d3d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18device/pci_device.c: Remove repeated wordElyes HAOUAS
Change-Id: Ia6936675684e3eaf2a57e2d28e465b1f0768249b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-12device/pci_device.c: Use same indents for switch/caseFelix Singer
Use same indents for switch/case to fix linter issues. Change-Id: I5c6abf5b918bac3df8d7617824392f2ec932cb32 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-10device: Add new Kconfig VGA_ROM_RUN_DEFAULT for mainboard userSubrata Banik
Platform can now select VGA_ROM_RUN_DEFAULT Kconfig to perform graphics initialization for PCI-E based discrete card through VGA OpRom (SoC or Mainboard user can't select VGA_ROM_RUN directly because it's part of choice option). (Note: Some payloads, like SeaBIOS, are also able to run Option ROMs, so coreboot does not need to enable VGA_ROM_RUN Kconfig) For payload like depthcharge, create VGA_ROM_RUN_DEFAULT Kconfig for mainboard to select design with DGPU where OpROM is embedded inside the DGPU card. Allow auto selection of VGA_ROM_RUN_DEFAULT from VGA_BIOS Kconfig. Also NO_GFX_INIT Kconfig to avoid running VGA_ROM_RUN by default in case SeaBIOS is used. TEST=Able to get Pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects VGA_ROM_RUN_DEFAULT. Change-Id: Iecb2fcdb105af449bc20ad727759cdef17d5e376 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28device/pnp: add register PNP_IO4Michael Niewöhner
Add the register PNP_IO4, which will be used by IT5570E in CB:48894. Change-Id: Ic820295247323f546d4c48ed17cfa4eab3dc5e92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48924 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28device + util/sconfig: introduce new device `gpio`Michael Niewöhner
Introduce a new device `gpio` that is going to be used for generic abstraction of gpio operations in the devicetree. The general idea behind this is that every chip can have gpios that shall be accessible in a very generic way by any driver through the devicetree. The chip that implements the chip-specific gpio operations has to assign them to the generic device operations struct, which then gets assigned to the gpio device during device probing. See CB:48583 for how this gets done for the SoCs using intelblocks/gpio. The gpio device then can be added to the devicetree with an alias name like in the following example: chip soc/whateverlake device gpio 0 alias soc_gpio on end ... end Any driver that requires access to this gpio device needs to have a device pointer (or multiple) and an option for specifying the gpio to be used in its chip config like this: struct drivers_ipmi_config { ... DEVTREE_CONST struct device *gpio_dev; u16 post_complete_gpio; ... }; The device `soc_gpio` can then be linked to the chip driver's `gpio_dev` above by using the syntax `use ... as ...`, which was introduced in commit 8e1ea52: chip drivers/ipmi use soc_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" ... end The IPMI driver can then use the generic gpio operations without any knowlege of the chip's specifics: unsigned int gpio_val; const struct gpio_operations *gpio_ops; gpio_ops = dev_get_gpio_ops(conf->gpio_dev); gpio_val = gpio_ops->get(conf->bmc_jumper_gpio); For a full example have a look at CB:48096 and CB:48095. This change adds the new device type to sconfig and adds generic gpio operations to the `device_operations` struct. Also, a helper for getting the gpio operations from a device after checking them for NULL pointers gets added. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-17azalia: Use `azalia_enter_reset` functionAngel Pons
Also tidy up some adjacent comments. Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17azalia: Use `azalia_exit_reset` functionAngel Pons
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17device/azalia_device.c: Add codec reset helpersAngel Pons
Many uses of `azalia_set_bits` are used to toggle the reset bit. To avoid having to repeat the register operations and the corresponding comment, create two helpers with self-explanatory names. They will be put to use in subsequent commits, with one change for each function. Change-Id: If0594fdaf99319f08a2e272cd37958f0f216e654 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17device/azalia_device.c: Clarify commentAngel Pons
The `4` here doesn't have to do with the size of u32. Instead, it is because the verb header contains the number of jacks, which is the number of four-verb groups. Change-Id: I3956ce5ec2a7abc29982504cf75b262a1c098af5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Replace `hda_find_verb` usesAngel Pons
This function is equivalent to `azalia_find_verb` in its current form, so replace them. Also, adapt and move the function description comment. Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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