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2009-04-22- printed CBFS rom address was always 0Stefan Reinauer
- drop dead code. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21Eliminate various issues brought up by scan-build.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06Some changes for option roms: Ronald G. Minnich
- don't make users pick the name. Names for option roms are in the v3-defined format of pci%04x,%04x.rom with the vendor and device id filling in the %04x. - users pass in vendor and device id. - users pass in a dest. If the dest is 0, the address of the ROM image in FLASH is returned. If the address is non-zero, then the decmpressor is called, and it will make sure the ROM image is copied to the destination (even in the uncompressed case). move qemu over to always using ROMFS Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06Add support for romfs to option rom loading. Ronald G. Minnich
Pretty simple: Find the rom in the romfs, if found, set dev properties so that the rest of the code works. At some point, we can remove some of the other code, i.e. the first else, and stop requiring people to do math. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-26During the suspend/resume programming I came to an issue that first 4KB ofRudolf Marek
memory must be clear with 0s because otherwise the resources of K8 will be totally messed up. res = probe_resource(dev, 0x100 + (reg | link)); This is called with dev = NULL and this is no good for probe_resource at all. The attached patch fixes the potential problems and of course the problem itself. On one particular place was missing test if the device really exists. This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check). The rest of the patch is just very paranoid and do all checkings. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Myles Watson <mylesgw@gmail.com> --This line, and those below, will be igno red-- M src/devices/pci_ops.c M src/northbridge/amd/amdk8/northbridge.c M src/northbridge/amd/amdfam10/northbridge.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-16fix typo in pci_device.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Fix mmconf (PCIe memory mapped config space access) support in v2. It wasStefan Reinauer
horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06fix a bunch of cast and type warnings and don't call the apic "nvram", thatStefan Reinauer
doesn't make no sense. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05If get_pbus() is called for a device which has no parent/ancestor busCarl-Daniel Hailfinger
with nonzero PCI bus operations, get_pbus() will get stuck in a silent endless loop. Detect the endless loop and break out with an error message. Such a situation can happen if the device tree is not yet initialized/walked completely. This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was used in early mainboard code for the AMD DBM690T. Instead, the code will now die() with a meaningful error message. Thanks to Ward Vandewege for testing my patches to track down that bug. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04I just went on a bugfix frenzy and fixed all printk format warningsCarl-Daniel Hailfinger
triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01Some changes required to get yabel working on v2 (and they generally makeStefan Reinauer
sense, too). Have one u64 instead of three. In order to use the old bios emulator, you have to do nothing. (Default, if CONFIG_PCI_ROM_RUN is enabled) In order to use yabel in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_YABEL default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 In order to use vm86 in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_VM86 default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09Remove some warnings, mainly from format strings which didn't match theMyles Watson
arguments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Backport all x86emu fixes from Pattrick Hueper to coreboot v2 (acked in v2,Stefan Reinauer
hence I consider it trivial in this case). This does not include the Yabel work. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Changes required to the device allocator:Stefan Reinauer
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE is set. - Mask moving bits to 32bit when resources are not supposed above 4G. Linux does not like this, even though the resource is disabled. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11From Vincent Legoll:Stefan Reinauer
Use dev_path() to have nice debug output patch is run-time tested Trivial, thus: Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01a heuristics is something different Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01Typo, thanks to Idwer for spotting this. (trivial patch)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01clarify in the printks what function is actually called. This little smart magicStefan Reinauer
drove me crazy during debugging. Fix Typos. Add a warning because the on-chipset devices are hardcoded. For newer machines, a lot more memory space will have special meanings, and we can't hardcode them all in an ifdef desert. (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typos and warnings in the device tree code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Fix so pci device memory allocation does not use memory base address at ↵Aaron Lwe
0xfec00000, this is reserved for APIC. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-28In pci_device.c, the class for VGA was not tested properly, leading toRonald Hoogenboom
no VGA output from coreboot, even after the boot-rom was executed properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the class field of struct device is '3 bytes: (base,sub,prog-if)'. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Torsten Duwe <duwe@lst.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-19 I'm attaching the patch which should fix both problems. Fix the Rudolf Marek
undefined u8 type and the bitpos selection in currently unused pnp_read_enable function. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, likeRudolf Marek
mine W83627EHF. This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but maps to original LDN and bit position in register 0x30. VirtualLDN = origLDN[7:0] | bitpos[10:8] Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-06Since a VGA console and the need to run any option ROMs areTorsten Duwe
rather independent, lift the implicit (broken) assumption that CONSOLE_VGA would also run the ROMs, and transfer it to a new config option VGA_ROM_RUN. This change is minimally intrusive, because all board configs that previously assumed CONSOLE_VGA would also run the ROMs didn't compile, they had to also specify PCI_ROM_RUN. Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen (separate ROM_RUN from VGA console). Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23fix a whole bunch of warnings. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23drop unused variable (and thus warning). trivial patch.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Add resource size and resource granularity reporting to device_util.c.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26Don't arbitrarily enable PERR# and SERR# for PCI devices. Marc Jones
It is platform specific. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.Yinghai Lu
For example: in C51/MCP55 or C51/MCP51 Will allow 1. C51 at 0x10 to 0x14, and MCP at 0 to 4 2. C51 at 1 to 4, and MCP at 7 to 0x0a The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it needed), and will prevent us from putting them on bus 0. Typical values for c51/mcp55 or c51/mcp51: HT_CHAIN_UNITID_BASE = 0x10 # for C51 HT_CHAIN_END_UNITID_BASE = 0 # for mcp If only have mcp with c51, HT_CHAIN_UNITID_BASE = 0 # for MCP #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20 Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12Generic driver for pretty much all known Standard Microsystems CorporationUwe Hermann
(SMSC) Super I/O chips. Most of the SMSC Super I/O chips seem to be similar enough (for our purposes) so that we can handle them with a unified driver. So far only the ASUS A8000 has been tested on real hardware! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21This is the last remainder from Yinghai's mega patch. It fixes issues withYinghai Lu
devices conflicting with the northbridge devices on PCI bus 0. Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22Add explicit license headers to all files in src/device.Uwe Hermann
For files derived from the Linux kernel we merely add a small header which states the origin of the file and the copyright owners of the modifications to the file. We know all files from Linux are licensed under the GPLv2. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09This patch corrects r2587. It makes sure that the VGA is initializedRoman Kononov
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1 Signed-off-by: Roman Kononov <kononov@dls.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06This patch makes sure that VGA is initialized before it is used. WithoutRoman Kononov
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough. Additionally, The VGA option rom will be executed if either CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1. Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27This change fixes a long-standing bug, whereby we do not set ret for anRonald G. Minnich
un-inited vector, which we should have done. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18fix old bug in the src/devices/pci_device.c Ronald G. Minnich
add devices for the lx and artecgroup/dbe61 point artecgroup at cs5536_lx as it is so different. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-22set up interrupt values for the southbridge, and add a function toRonald G. Minnich
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18add option to decide to use onboard vga or addon card.Yinghai Lu
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-24hex values with 0x prefixStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-11this was in my queue since 2005/10/26Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-17- sc520 updates. move PAR setup to mainboard auto.cStefan Reinauer
- some ts5300 code. Let's push this upstream for now. - fix a typo in device.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-17TypoRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-17First, a FATAL error, that blows up your BIOS, should NEVER FAIL to Ronald G. Minnich
provide more information. The printk_debug in that failure case is now a printk_error. The msm stuff is for debugging. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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