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path: root/src/drivers/i2c
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2016-11-07drivers/i2c/tpm/cr50: Increase IRQ timeoutDuncan Laurie
Increase the IRQ timeout to prevent issues if there is a delay in the TPM responding to a command. Split the no-IRQ case out so it doesn't suffer unnecessarily. BUG=chrome-os-partner:59191 TEST=suspend/resume testing on eve board Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17204 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17092 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25drivers/i2c/generic: Re-factor SSDT generation codeFurquan Shaikh
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17089 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25drivers/i2c/generic: Enable support for adding PowerResource for deviceFurquan Shaikh
Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. 2. Reset delay - Delay after reset GPIO is de-asserted (default 0). 3. Enable GPIO - Optional, GPIO to enabled device. 4. Enable delay - Delay after enable GPIO is asserted (default 0). BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17081 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-24drivers/i2c/generic: Return correct name for acpi_nameFurquan Shaikh
Return config->name if it is not NULL. BUG=chrome-os-partner:55988 Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17077 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07src/drivers: Remove whitespace after memcpy & memsetElyes HAOUAS
Change-Id: If79eb706b6d44f7c34dfe31a1545f5850870b334 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16866 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07Gale: Fix the orange color to match the UX docSuresh Rajashekara
UX Doc = go/gale-hw-ui This color wasn't changed earlier as the change wasn't done in the OS also. However, since we cannot change this later in FW (but OS can change anytime), I am making this change after discussing with the UX team. BUG=b:31501528, b:31633562 TEST=Change the device state to 'recovery mode' to observe the new color. BRANCH=none Change-Id: Ia91f14eb77492095cb41a9de0bb9790e72aa4851 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 36a3d8c6eabbc0b23d0a15d5bddc5ed3bdeebe70 Original-Change-Id: I88768b94cf91804a6005e44b1a168e059698ec4b Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388206 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Christopher Book <cbook@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/16767 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06i2c/ww_ring: LED changes as per UX team feedback.Suresh Rajashekara
Colors and patterns as defined by the UX team BUG=b:31501528 TEST=Move the device to different states in FW using rec and dev button and verify the colors BRANCH=None Change-Id: I66d41a54590cd3ce4e5202c7cfa890f462fe195e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 703559d5dddaeeb7d435d6cadbb2009a1b7a76c8 Original-Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7 Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387258 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Christopher Book <cbook@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/16718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06i2c/ww_ring: Change LED configuration for Gale EVT3Suresh Rajashekara
Gale EVT3 has only one LED controller (earlier we had 2). Remove the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the different colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/16697 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-05drivers/i2c/tpm/cr50: Initialize IRQ status handler before probeDuncan Laurie
Move the setup of the IRQ status handler so it will be set up properly before the early probe happens. BUG=chrome-os-partner:53336 Change-Id: I4380af1233d2a252899459635a3cb69ca196088d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16861 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-28drivers/i2c/generic: Add config for marking device as probedDuncan Laurie
Add a config option to the generic I2C device driver to indicate to the OS that this device should be probed before being added. This can be used to provide ACPI device instantiations to devices that may not actually exist on the board. For example, if multiple trackpad vendors are supported on the same board they can both be described in ACPI and the OS will probe the address and load the driver only if the device responds to the probe at that address. BUG=chrome-os-partner:57686 Change-Id: I22cffb4b15f25d97dfd37dc58bca315f57bafc59 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Support interrupts for statusDuncan Laurie
Support reading the ACPI GPE status (on x86) to determine when the cr50 is ready to return response data or is done processing written data. If the interrupt is not defined by Kconfig then it will continue to use the safe delay. This was tested with reef hardware and a modified cr50 image that generates interrupts at the intended points. BUG=chrome-os-partner:53336 Change-Id: Ic8f805159650c45382cacac8840450a1f8b4d7a1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Improve data handling and function namesDuncan Laurie
Unify the function names to be consistent throughout the driver and improve the handling while waiting for data available and data expected flags from the TPM. BUG=chrome-os-partner:53336 Change-Id: Ie2dfb7ede1bcda0e77070df945c47c1428115907 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16668 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up locality functionsDuncan Laurie
Clean up the mask and timeout handling in the locality functions that were copied from the original driver. BUG=chrome-os-partner:53336 Change-Id: Ifdcb3be0036b2c02bfbd1bcd326e9519d3726ee0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16667 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Rename i2c read/write functionsDuncan Laurie
Rename the low-level functions from iic_tpm_read/write to cr50_i2c_read/write to better match the driver name, and pass in the tpm_chip structure to the low-level read/write functions as it will be needed in future changes. BUG=chrome-os-partner:53336 Change-Id: I826a7f024f8d137453af86ba920e0a3a734f7349 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16666 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Clean up timeoutsDuncan Laurie
Use two different timeouts in the driver. The 2ms timeout is needed to be safe for cr50 to cover the extended timeout that is seen with some commands. The other at 2 seconds which is a TPM spec timeout. BUG=chrome-os-partner:53336 Change-Id: Ia396fc48b8fe6e56e7071db9d74561de02b5b50e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm/cr50: Reduce max buffer sizeDuncan Laurie
Reduce the static buffer size from the generic default 1260 down to 64 to match the max FIFO size for the cr50 hardware and reduce the footprint of the driver. BUG=chrome-os-partner:53336 Change-Id: I6f9f71d501b60299edad4b16cc553a85391a1866 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Split cr50 driver from main driverDuncan Laurie
Originally I thought it would be cleaner to keep this code in one place, but as things continue to diverge it ends up being easier to split this into its own driver. This way the different drivers in coreboot, depthcharge, and the kernel, can all be standalone and if one is changed it is easier to modify the others. This change splits out the cr50 driver and brings along the basic elements from the existing driver with no real change in functionality. The following commits will modify the code to make it consistent so it can all be shared with depthcharge and the linux kernel drivers. BUG=chrome-os-partner:53336 Change-Id: I3b62b680773d23cc5a7d2217b9754c6c28bccfa7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21drivers/i2c/tpm: Move common variables to headerDuncan Laurie
Move the common enums and variables to tpm.h so it can be used by multiple drivers. BUG=chrome-os-partner:53336 Change-Id: Ie749f13562be753293448fee2c2d643797bf8049 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16662 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19Revert "drivers/i2c/tpm: Move common variables to header"Duncan Laurie
This reverts commit 64df72e8e2d1c086705325533767ca5e201e842a.
2016-09-19Revert "drivers/i2c/tpm: Split cr50 driver from main driver"Duncan Laurie
This reverts commit c565f9910707b91fcc7a27bab28806e558bb474d.
2016-09-19Revert "drivers/i2c/tpm/cr50: Reduce max buffer size"Duncan Laurie
This reverts commit 97a2a1ece152b6d40a524361721405b77c37959d.
2016-09-19Revert "drivers/i2c/tpm/cr50: Clean up timeouts"Duncan Laurie
This reverts commit 93c778688f0bf2f90334505a3082a2cd4ce1623a.
2016-09-19Revert "drivers/i2c/tpm/cr50: Rename i2c read/write functions"Duncan Laurie
This reverts commit 6f5ceb26b9b3e1455ebbd6192e1d2c832bddc77e.
2016-09-19Revert "drivers/i2c/tpm/cr50: Clean up locality functions"Duncan Laurie
This reverts commit 557e1a729a9ca89e814220b6203b7ac0dc446913.
2016-09-19Revert "drivers/i2c/tpm/cr50: Improve data handling and function names"Duncan Laurie
This reverts commit 1241e7db55aff313e56bf4546d969c11368b08a2.
2016-09-19Revert "drivers/i2c/tpm/cr50: Support interrupts for status"Duncan Laurie
This reverts commit a5e419c51187d24818f056327746a18676fe3a20.
2016-09-19drivers/i2c/tpm/cr50: Support interrupts for statusDuncan Laurie
Support reading the ACPI GPE status (on x86) to determine when the cr50 is ready to return response data or is done processing written data. If the interrupt is not defined by Kconfig then it will continue to use the safe delay. This was tested with reef hardware and a modified cr50 image that generates interrupts at the intended points. BUG=chrome-os-partner:53336 Change-Id: I9f78f520fd089cb4471d8826a8cfecff67398bf8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Improve data handling and function namesDuncan Laurie
Unify the function names to be consistent throughout the driver and improve the handling while waiting for data available and data expected flags from the TPM. BUG=chrome-os-partner:53336 Change-Id: I7e3912fb8d8c6ad17d1af2d2a7189bf7c0c52c8e Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Clean up locality functionsDuncan Laurie
Clean up the mask and timeout handling in the locality functions that were copied from the original driver. BUG=chrome-os-partner:53336 Change-Id: Ifa1445224b475aec38c2ac56e15cb7ba7fcd21ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Rename i2c read/write functionsDuncan Laurie
Rename the low-level functions from iic_tpm_read/write to cr50_i2c_read/write to better match the driver name, and pass in the tpm_chip structure to the low-level read/write functions as it will be needed in future changes. BUG=chrome-os-partner:53336 Change-Id: Ib4a68ce1b3a83ea7c4bcefb9c6f002f6dd4aac1f Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Clean up timeoutsDuncan Laurie
Use two different timeouts in the driver. The 2ms timeout is needed to be safe for cr50 to cover the extended timeout that is seen with some commands. The other at 2 seconds which is a TPM spec timeout. BUG=chrome-os-partner:53336 Change-Id: I77fdd7ea646b8b2fef449f07e3a08bcce174fe8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Reduce max buffer sizeDuncan Laurie
Reduce the static buffer size from the generic default 1260 down to 64 to match the max FIFO size for the cr50 hardware and reduce the footprint of the driver. BUG=chrome-os-partner:53336 Change-Id: Ia88facca607f3fd5072d0d986323fde075f15855 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm: Split cr50 driver from main driverDuncan Laurie
Originally I thought it would be cleaner to keep this code in one place, but as things continue to diverge it ends up being easier to split this into its own driver. This way the different drivers in coreboot, depthcharge, and the kernel, can all be standalone and if one is changed it is easier to modify the others. This change splits out the cr50 driver and brings along the basic elements from the existing driver with no real change in functionality. The following commits will modify the code to make it consistent so it can all be shared with depthcharge and the linux kernel drivers. BUG=chrome-os-partner:53336 Change-Id: Ia9a65e72519b95f5739e3b7a16b9c2431d64ebe2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm: Move common variables to headerDuncan Laurie
Move the common enums and variables to tpm.h so it can be used by multiple drivers. BUG=chrome-os-partner:53336 Change-Id: I0febe98620d0ddd4ec6b46cd3073e48c12926266 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-14drivers/i2c/tpm: Clean up handling of command readyDuncan Laurie
The TPM driver was largely ignoring the meaning of the command ready bit in the status register, instead just arbitrarily sending it at the end of every receive transaction. Instead of doing this have the command ready bit be set at the start of a transaction, and only clear it at the end of a transaction if it is still set, in case of failure. Also the cr50 function to wait for status and burst count was not waiting the full 2s that the existing driver does so that value is increased. Also, during the probe routine a delay is inserted after each status register read to ensure the TPM has time to actually start up. Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-08drivers/i2c/tpm: Fix early TPM probeDuncan Laurie
The early TPM probe was done directly in tis.c ignoring the lower layer that provides appropriate access to the chip. Move this into a tpm_vendor_probe() function so it can use iic_tpm_read() with all of the built-in delays and semantics instead of calling i2c_readb() directly from the wrong layer. This fixes early init failures that were seen with the cr50 i2c tpm on the reef mainboard. Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Fix error handling for tis structure not initializedDuncan Laurie
If the TPM completely fails to respond then the vendor structure may not have assigned handlers yet, so catch that case and return error so the boot can continue to recovery mode instead of asserting over and over. Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Add support for generating ACPI tableDuncan Laurie
Add code to generate an ACPI descriptor for an I2C TPM based on the device as described in devicetree.cb. This currently requires the devicetree to provide the HID, since we don't currently talk to the TPM in ramstage and I didn't want to add yet another init path for it here. This was tested on a reef board to ensure that the device is described properly in the SSDT. Change-Id: I43d7f6192f48e99a4074baa4e52f0a9ee554a250 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16397 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06drivers/i2c/tpm: Add support for cr50 TPMDuncan Laurie
Add support for the cr50 TPM used in apollolake chromebooks. This requires custom handling due to chip limitations, which may be revisited but are needed to get things working today. - timeouts need to be longer - must use the older style write+wait+read read protocol - all 4 bytes of status register must be read at once - same limitation applies when reading burst count from status reg - burst count max is 63 bytes, and burst count behaves slightly differently than other I2C TPMs - TPM expects the host to drain the full burst count (63 bytes) from the FIFO on a read Luckily the existing driver provides most abstraction needed to make this work seamlessly. To maximize code re-use the support for cr50 is added directly instead of as a separate driver and the style is kept similar to the rest of the driver code. This was tested with the cr50 TPM on a reef board with vboot use of TPM for secdata storage and factory initialization. Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16396 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-06drivers/i2c/tpm: Allow sleep durations to be set by the chipDuncan Laurie
Allow the sleep durations used by the driver to be set by the specific chip so they can be tuned appropriately. Since we need to read the chip id to know the values use very conservative defaults for the first command and then set it to the current values by default. Change-Id: Ic64159328b18a1471eb06fa8b52b589eec1e1ca2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16395 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Make driver safe for use in x86 pre-ramDuncan Laurie
Use CAR accessors where needed for accessing static data. In some cases this required some minor restructuring to pass in a variable instead of use a global one. For the tpm_vendor_init the structure no longer has useful defaults, which nobody was depending on anyway. This now requires the caller to provide a non-zero address. Tested by enabling I2C TPM on reef and compiling successfully. Change-Id: I8e02fbcebf5fe10c4122632eda1c48b247478289 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02i2c/w83795: Fix chip type messagePatrick Georgi
(val & 4) == 1 is always false. Since val & 4 is either zero or non-zero, just drop the second test (for "== 1"). Validated against the data sheet that this is really the right register, bit and value. Change-Id: I627df9a9b4fddfff486689e405f52a3b54135eef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241864 Reviewed-on: https://review.coreboot.org/16009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31src/drivers: Capitalize CPU, RAM and ACPIElyes HAOUAS
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28i2c/ww_ring: Add ww_ring files to ramstageFurquan Shaikh
These files are required by storm and gale boards for enabling elog support in ramstage. BUG=chrome-os-partner:55639 Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-14drivers/i2c: Add new driver for RTC type PCF8523Werner Zeh
This driver enables the usage of an external RTC chip PCF8523 which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in device tree so that the used setup can be adapted in device tree to match the configuration of the device on the mainboard. Change-Id: I2d7e161c9e12b720ec4925f1acfd1dd8ee6ee5f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15641 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-08drivers/i2c/da7219: Add driver for generating device in SSDTDuncan Laurie
Add a device driver to generate the device and required properties into the SSDT. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. This was tested on the reef mainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object. Change-Id: Ia809e953932a7e127352a7ef193974d95e511565 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23kconfig: allow various tpm type and interface permutationsVadim Bendebury
Until now it was assumed that all TPM devices were of the same type (TCG 1.2 spec compliant) and x86 based boards had LPC connected TPMs and all other boards had I2C connected TPMs. With the advent of TPM2 specification there is a need to be able to configure different combinations of TPM types (TPM or TPM2) and interfaces (LPC, I2C and SPI). This patch allows to do it. Picking Chrome OS still assumes that the board has a TPM device, but adding MAINBOARD_HAS_TPM2 to the board's Kconfig will trigger including of TPM2 instead. MAINBOARD_HAS_LPC_TPM forces the interface to be set to LPC, adding SPI_TPM to the board config switches interface choice to SPI, and if neither of the two is defined, the interface is assumed to be I2C. BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that none of the generated board configurations change as a result of this patch. With the rest of the stack in place it is possible to configure different combinations of TPM types and interfaces for ARM and x86 boards. Change-Id: I24f2e3ee63636566bf2a867c51ed80a622672f07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5a25c1070560cd2734519f87dfbf401c135088d1 Original-Change-Id: I659e9301a4a4fe065ca6537ef1fa824a08d36321 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349850 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15294 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>