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path: root/src/drivers/intel/fsp1_1/after_raminit.S
AgeCommit message (Expand)Author
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
2016-02-02soc/intel/common: Use SoC specific routine to read/write MTRRsLee Leahy
2016-01-29intel/skylake: Implement native Cache-as-RAM (CAR)Subrata Banik
2015-12-03intel/fsp: Add post codes for FSP phasesDuncan Laurie
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
2015-10-14fsp1_1: add verstage supportAaron Durbin
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin