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2018-08-10src/drivers: Fix typoElyes HAOUAS
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17security/vboot: Add interface for FSP 2.0 mrc cachingPhilipp Deppenwiese
* Move vboot/tpm specific implementation to vboot. * Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set. * Preparation for software hash function support, no logic changed. Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24904 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28drivers/intel/fsp2_0: Fix uncountable "information"Elyes HAOUAS
Change-Id: I91e13a786b12328f1d9200f76788faa19847bbe7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25drivers/intel/fsp2_0: Make use of xmalloc for FSP-S UPDSubrata Banik
Don't allocate FSP-S UPD over stack. This patch reduces stack usage for Cannonlake platform. TEST=On CNL platform stack usage reduces from ~3.6KiB to ~1KiB. Change-Id: I07ef0db6720d7e6865ac1641ce2661009332907c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26501 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01drivers/intel/fsp2_0: Include MP services header for UDK2017 supported platformSubrata Banik
BRANCH=none BUG=b:74436746 TEST=Able to include EFI_MP_SERVICES_PPI without any error. Change-Id: I5add8e533dfd3f6d03abf7b2ca1a83f81f1c5920 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-26drivers/intel/fsp: Fix TPM initialization when vboot is disabledYouness Alaoui
A change introduced by commit fe4983e5 [1] in order to prevent re-initialization of the TPM if already set up in verstage had the wrong logic in the if statement, causing the TPM to never be initialized if vboot is disabled. The RESUME_PATH_SAME_AS_BOOT config is enabled by default for ARCH_X86, resulting in the if statement to always evaluate to false. Remove that condition from the if statement to allow it to function as intended. This patch also enables TPM initialization for FSP 2.0 with the same conditions. [1] intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage https://review.coreboot.org/#/c/coreboot/+/14106/ Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23680 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selectedSubrata Banik
This patch fixes brokenness issues in coreboot with CONFIG_DISPLAY_HOBs config selection due to recent UDK2017 package changes. TEST=Build and boot UDK2017 platforms with DISPLAY_HOBS select. Change-Id: I5c779c86870c62253d64c6af456bf017553e269c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-09drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driverSubrata Banik
As per FSP 2.0 specification and FSP SOC integration guide, its not expected that SMBIOS Memory Information GUID will be same for all platform. Hence fsp_find_smbios_memory_info() function inside common/driver code is not generic one. Removing this function and making use of fsp_find_extension_hob_by_guid() to find SMBIOS Memory Info GUID from platform code as needed. Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31drivers/intel/fsp2_0: Add support to display FSP version info HobSubrata Banik
This patch locates FSP FVI hob in order to extract all firmware ingredient version information. So far this feature is only supported for CannonLake SoC onwards. Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Make use of Resource Type macro from EDK codeSubrata Banik
Users are getting build error due to duplicate macro definitions of same resource type between fsp driver code and UEFI headers. Hence this patch ensures to refer a single source location for macro definitions to avoid compilation error. Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-11intel/fsp2_0: Set boot mode default as per s3wake statusAamir Bohra
Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data validity. With current implementation in S3 resume path, if mrc cache data is invalid, the bootmode is not updated further and remains set at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get incorrect boot mode context and reinitialize memory in S3 resume path. In correct flow fspm should have correct bootmode context i.e. S3 resume and return error in case mrc cache data is invalid or not found. BUG=b:70973961 BRANCH=None TEST=Verify correct bootmode is set on S3 resume, even when mrc cache data is invalid. Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/23156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-11intel/fsp2_0: Issue hard reset in S3 resume for invalid mrc cache dataAamir Bohra
In S3 resume, for cases if valid mrc cache data is not found or RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION. This gets memory to be retrained in S3 flow. Data context including that of imdr root pointer would be lost, invoking a hard reset in romstage post memory init. Issuing hard reset before memory init, saves fsp memory initialization and training overhead. BUG=b:70973961 BRANCH=None TEST=Verify S3 resume flows on soraka. Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-17drivers/mrc_cache: move mrc_cache support to driversAaron Durbin
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03drivers/intel/fsp2_0/hob_verify: Correct conversion specifierPaul Menzel
Use the correct conversion specifier for `size_t` to fix the error below. ``` src/drivers/intel/fsp2_0/hob_verify.c:31:4: error: format '%lx' expects \ argument of type 'long unsigned int', but argument 4 has type \ 'size_t {aka unsigned int}' [-Werror=format=] "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", ^ range_entry_size(&tolum), cbmem_overhead_size()); ~~~~~~~~~~~~~~~~~~~~~ ``` Found-by: gcc (Debian 7.2.0-8) 7.2.0 Change-Id: I4631672211095f9934925e9bd230ccbf63c736af Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-06soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbtPatrick Georgi
All callers of locate_vbt just care about the file content and immediately map the rdev for its content. Instead of repeating this in all call sites, move that code to locate_vbt. Change-Id: I5b518e6c959437bd8f393269db7955358a786719 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05drivers/intel/fsp2_0: use common code to fetch vbt.binPatrick Georgi
No need for having two of everything in the coreboot codebase. Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLESubrata Banik
This patch to ensure that coreboot is able to store memory training data into SPI and perform platform lockdown after PCI enumeration is done before handing over control to NotifyPhase() - Post PCI enumeration. Modified coreboot bootstate execution order below: BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration TEST=Please find test case and results for Chrome Devices as Apollolake- Reef, Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS. 1. Without patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Chrome CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. 2. With patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Yocto CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there is no noticeable difference. On a reboot, suspend resume from Chrome console, the mrc cache is found, and utilized. Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17arch/x86: Make postcar TempRamExit call genericMarshall Dawson
Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10fsp2_0/mma: Enable EvLoader in FSP for MMAPratik Prajapati
EvLoader is FSP module which loads and runs MMA tests. With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader needs to be enabled with UPD param from coreboot. Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25drivers/intel/fsp2_0: Add NULL check while locating hob list ptrSubrata Banik
Assert incase unable to locate hob list pointer due to cbmem is not available. Change-Id: I17f54b07ab149ae06d09226ed9063189d829efe2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17intel/fsp: Add and use new post codes for FSP phase indicationSubrata Banik
New post codes are POST_FSP_MEMORY_EXIT POST_FSP_SILICON_EXIT This patch will make it more consistent to debug FSP hang and reset issues. Bug=none Branch=none TEST=Build and Boot on eve Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18coreboot_tables: specify clear interface for lb_framebuffer()Aaron Durbin
For some reason the "interface" for adding framebuffer information is sitting in src/include/vbe.h while also guarding the call to fill_lb_framebuffer() with vbe_mode_info_valid() along with some macro if CONFIG_* for good measure. Move the fill_lb_framebuffer() declaration to coreboot_tables.h and provide a comment about how it should be used. Also, now that there's no need for the notion of a global vbe_mode_info_valid() remove it from the conditional call path of fill_lb_framebuffer(). Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-28drivers/intel/fsp2_0: add option to incorporate platform memory versionAaron Durbin
On Chrome OS systems a memory setting change is needed to be deployed without updating the FSP blob proper. Under such conditions one needs to trigger retrain of the memory. For ease of use provide an option, FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC and mainboard memory setting version number into the FSP version passed to the platform. The lower 8 bits of the FSP version are the build number which in practice is normally 0. Use those 8 bits to include the SoC and mainboard memory settings version. When FSP, SoC, or mainboard memory setting number is bumped a retrain will be triggered. BUG=b:37687843 Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19452 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10drivers/intel/fsp2_0: Switch from binary to decimalLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Avoid gcc v4.3+ binary constant extension: TEST=Build and run on Galileo Gen2 Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18747 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18746 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space prohibited before open square bracket '[' ERROR: spaces required around that ':' (ctx:VxE) TEST=Build and run on Galileo Gen2 Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18744 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Add space before *Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "(foo*)" should be "(foo *)" False positives are generated by checkpatch for the following condition which is not properly detecting the variable type: ERROR: need consistent spacing around '*' (ctx:WxV) The false positives are found in debug.h and upd_display.c TEST=Build and run on Galileo Gen2 Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Use tabs for indentLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp loadFurquan Shaikh
Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed. BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully. Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API supportBrenton Dong
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11drivers/intel/fsp2_0: Include stddef.h in soc_binding.hFurquan Shaikh
soc_binding.h includes FSP headers which define NULL macro. Because of this, including stddef.h after soc_binding.h results in NULL being re-defined. Thus, include stddef.h in soc_binding.h to avoid having users include stddef.h along with soc_binding.h. Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17773 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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