summaryrefslogtreecommitdiff
path: root/src/drivers/intel
AgeCommit message (Collapse)Author
2016-12-19drivers/intel/gma: Use scaling to simplify fb configNico Huber
Utilize libgfxinit's support for scaling to simplify the framebuffer configuration. In case of multiple displays of different resolutions, we had configured one framebuffer big enough for their union, each display only showing its respective upper left window. Instead, we use the smallest resolution now and show the whole image on all displays. Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17492 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-12-19drivers/intel/gma: Add textmode support with libgfxinitNico Huber
Add an alternative gfxinit implementation for textmode. The legacy VGA plane and textmode is configured through coreboot provided functions. libgfxinit uses this plane as alternative to the usual high resolution plane. Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17279 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11drivers/intel/fsp2_0: Include stddef.h in soc_binding.hFurquan Shaikh
soc_binding.h includes FSP headers which define NULL macro. Because of this, including stddef.h after soc_binding.h results in NULL being re-defined. Thus, include stddef.h in soc_binding.h to avoid having users include stddef.h along with soc_binding.h. Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17773 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30driver/intel/fsp2_0: Add version parameter to FSP platform callbackAndrey Petrov
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29drivers/intel/gma: Hook up libgfxinitNico Huber
Add `libgfxinit` as another option for native graphics initialization. For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has to be called by the respective northbridge/soc code. A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and implement the Ada package `GMA.Mainboard` with a single function `ports` that returns a list of ports to be probed for displays. v2: Update 3rdparty/libgfxinit to its latest master commit to make things buildable within coreboot. v3: Another update to 3rdparty/libgfxinit. Including support to select the I2C port for VGA. Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-21drivers/intel/fsp2_0: Check for NULL before using pointerMartin Roth
The cbmem routines pass back NULL on error. Check for this before using the pointer. Addresses coverity issue 1365731 - Dereference null return value Change-Id: I92995366ffb15afd0950b9a8bbb6fe16252b2c38 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17480 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21fsp2_0: implement stage cache for silicon initBrandon Breitenstein
Stage cache will save ~20ms on S3 resume for apollolake platforms. Implementing the cache in ramstage to save silicon init and reload it on resume. This patch adds passing S3 status to silicon init in order to verify that the wake is from S3 and not for some other reason. This patch also includes changes needed for quark and skylake platforms that require fsp 2.0. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for reef and tested boot and S3 resume path saving 20ms Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/17460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18intel post-car: Increase stacktop alignmentKyösti Mälkki
Align top of stack to 8 bytes, value documented as FSP1.1 requirement. Also fix some cases of uintptr_t casted to unsigned long. Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17461 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-12drivers/intel/fsp2_0: track end of firmware notificationsAaron Durbin
The end of firmware notification is currently not being tracked so it's hard to get good data on how long it takes. Update the code to provide timestamp data as well as post codes. BUG=chrome-os-partner:56656 Change-Id: I74c1043f2e72d9d85b23a99b8253ac465f62a7f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17373 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-11lib/tlcl: Ensure tlcl library is initialized only onceFurquan Shaikh
Since tlcl library is used other than just vboot driver, ensure that the library is initialized only once per stage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified in recovery mode on reef, tlcl library is initialized only once in romstage. Change-Id: I6245fe9ed34f5c174341b7eea8db456b45113287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17364 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10drivers/intel/fsp2_0: Add support for recovery MRC hash space in TPMFurquan Shaikh
This space is read/updated only in recovery mode. 1. During read phase, verify if the hash of MRC data read from RECOVERY_MRC_CACHE matches the hash stored in TPM. 2. During update phase, calculate hash of training data returned by MRC and save it in TPM. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified MRC data hash comparison and update operation on reef. Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10mrc: Add support for separate training cache in recovery modeFurquan Shaikh
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot modes. Check if both are present under one unified region and protect that region as a whole. Else try protecting individual regions. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27driver/intel/fsp2_0: Reset on invalid stage cache.Naresh G Solanki
Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is invalid during S3 resume. Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-09drivers/intel/wifi: Add depends on ARCH_X86Martin Roth
When compiling a non-x86 platform with DRIVERS_INTEL_WIFI enabled, we get the build error: src/drivers/intel/wifi/wifi.c:17:30: fatal error: arch/acpi_device.h: No such file or directory acpi_device.h only exists in the x86 architecture directory. Change-Id: Id0e29558336bf44e638cfcb97c22f31683ea4ec7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16906 Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-10-07soc/intel/apollolake: Implement stage cache to improve resume timeBrandon Breitenstein
This patch enables stage cache to save ~40ms during S3 resume. It saves ramstage in the stage cache and restores it on resume so that ramstage does not have to reinitialize during the resume flow. Stage cache functionality is added to postcar stage since ramstage is called from postcar. BUG=chrome-os-partner:56941 BRANCH=none TEST=built for Reef and tested ramstage being cached Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16833 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-07src/drivers: Remove whitespace after memcpy & memsetElyes HAOUAS
Change-Id: If79eb706b6d44f7c34dfe31a1545f5850870b334 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16866 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30Kconfig: Prefix hex defaults with 0xMartin Roth
Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16827 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30drivers/intel/fsp2_0: Fix debug display supportLee Leahy
Fix errors in debug display support. BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug on) and run on Galileo Gen2 Change-Id: I2ece056d66dc8568a7b7206970f20368ec5bf147 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16809 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-27intel/gma/vbt.c: pad the ID string with spaces.Arthur Heymans
The VBT id string is 20 characters long. If the string is shorter than 20 it needs spaces at the end. This change is cosmetic as all strings were padded by hand. Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-19driver/intel/fsp1_1: Utilise soc/intel/common for adding vbt.binNaresh G Solanki
Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common instead to add vbt.bin in cbfs. Also, VBT blob is added to CBFS as RAW type hence when walking the CBFS to find vbt.bin, search with type as RAW. Change-Id: I08f2556a34f83a0ea2b67b003e51dcace994361b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16610 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15driver/intel/fsp20: move lb_framebuffer functionNaresh G Solanki
move lb_framebuffer function in soc/intel/apollolake to driver/intel/fsp20 so that fsp 2.0 bases soc's can use common lb_framebuffer function. Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-15driver/intel/fsp2_0: Make FSP-M binary XIPRizwan Qureshi
If FSP_M_XIP is selected, then relocate FSP-M binary while adding it in CBFS so that it can be executed in place. Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12driver/fsp2_0: Include stdint header file in api.hNaresh G Solanki
'bool' type is reported undefined due to missing stdint.h inclusion, Fix it by including the same. Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-08intel/gma: Use defines for registers and values in edid.cSebastian "Swift Geek" Grzywna
This replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/16339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-02apollolake: relocate fsp header files to vendorcodeBrandon Breitenstein
FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31src/drivers: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16321 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31driver/intel/fsp2.0: Add External stage cache region helperRizwan Qureshi
If ramstage caching outside CBMEM is enabled i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a helper function to determine the caching region in SMM should be implemented. Add the same to FSP2.0 driver. FSP1.1 driver had the same implementation hence copied stage_cache.c. The SoC code should implement the smm_subregion to provide the base and size of the caching region within SMM. The fsp/memmap.h provides the prototype and we will reuse the same from FPS 1.1. Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16312 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-20drivers/intel/fsp2_0: Add SMBIOS memory HOB supportRavi Sarawadi
Add SMBIOS memory GUID and functions to retrieve HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ie7e2239bb691c748d9fd852c3dc8cdc05243b164 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-12drivers/intel/fsp2_0: Fix FSP reset pathLee Leahy
Don't verify HOB list pointer or HOBs when FSP returns a reset request. BRANCH=none BUG=chrome-os-partner:56159 TEST=Build and run on Galileo Gen2. Change-Id: I6382f5ff92092623955806ebff340608c4ee156a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11intel/fsp1_1: Use new per-region position overridePatrick Georgi
It cooperates better with the file sorting heuristic. Change-Id: I1c071243720352970dd2c4c2afed12451f91dcaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16141 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10drivers/intel/fsp2_0: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: If7bfcea1af82209dcdc5a9f9f2d9334842c1595e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10drivers/intel/fsp1_1: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: Ib01aef448798e47ac613b38eb20bf25537b9221f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-06drivers/intel/fsp1_1: only set a base address for FSP in COREBOOT CBFSAaron Durbin
The -b FSP_LOC argument to cbfstool is only valid for the COREBOOT CBFS. Don't pass that value for all other CBFS regions. Change-Id: Ib5321e7a7dbee8d26eb558933c8ce3fea50b11fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05drivers/intel/fsp2_0: Ensure EC is in right mode before memory initFurquan Shaikh
If EC_GOOGLE_CHROMEEC is enabled, ensure that the EC is in correct mode before running memory init. This saves additional memory training required in recovery path because of reboot later in ramstage. BUG=chrome-os-partner:54245 Change-Id: Ic71c054afdcd0001cea95563fe513783b56f3e60 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05drivers/intel/fsp2_0: Add checklist supportLee Leahy
Add the Kconfig value to point to the checklist data files. TEST=Build and run on Galileo Gen2 Change-Id: I3737b46162214fad139382193de944ec5d175645 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16039 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03drivers/intel/fsp2_0: Update the debug levelsLee Leahy
Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Remove fsp_print_upd_info declarationLee Leahy
Remove unused function declaration. TEST=Build and run on Galileo Gen2 Change-Id: Id971829c19c2535c975a68c44fb3697f60d0b4ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Disable display of FSP headerLee Leahy
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Handle FspNotify callsLee Leahy
Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. Display the MTRRs before the first call to fsp_notify. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: FSP driver handles all FSP errorsLee Leahy
Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInitLee Leahy
Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15850 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add display HOB supportLee Leahy
Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into util.h * Move hob_type enum into util.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 00:34:59 +0000