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2018-11-27src/{commonlib,drivers/intel/fslp1_1/include}: Fix typoFrans Hendriks
Correct typo of 'compilation' BUG=N/A TEST=N/A Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-11-26drivers/intel/fsp1_1/raminit.c: Report only when NVS HOB is missingFrans Hendriks
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always. This hob is only generated by FSP during non-S3 and MRC data is changed. Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is required. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang Jin <huang.jin@intel.com>
2018-11-23soc/intel/skylake: Drop FSP_CAR optionsNico Huber
It's not implemented for Skylake, all combinations that try to enable it either result in Kconfig or linker errors. Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's effective. TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default configs with and without this patch: binaries stay the same. Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-23soc/intel/common: Bring DISPLAY_MTRRS into the lightNico Huber
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.SFrans Hendriks
soc/car_setup.S is included when SKIP_FSP_CAR is enabled, but no chipset/SoC have car_setup.S available. Remove include and post_code() call always solving build errors. BUG=NA TEST=NA Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang Jin <huang.jin@intel.com>
2018-11-22src/drivers/intel/fsp1_1/Kconfig: Remove unused FSP_USES_UPDFrans Hendriks
CONFIG_FSP_USES_UPD is not used by FSP 1.1. Remove this config from this file. BUG=N/A TEST=Intel CherryHill CRB Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang Jin <huang.jin@intel.com>
2018-11-22soc/drivers/intel/fsp1_1: Always report returned status of FspTempRamInit()Frans Hendriks
Returned status code FspTempRamInit() is not displayed when error occurs. Move the printk() call before the check for status. BUG=NA TEST=Portwell PQ7-M107 Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29695 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Huang Jin <huang.jin@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29303 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-15drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATAElyes HAOUAS
Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-07drivers/intel/fsp2_0: Run SplitFspBin with python2Nico Huber
It's not Python 3 compatible. Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-22intel: Use CF9 reset (part 2)Patrick Rudolph
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18drivers/intel/fsp*: Use newly added post codes for memory param prepFurquan Shaikh
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to search from where these post codes are generated during boot flow. Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init to make it consistent with fsp1_1 memory init. Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-17drivers/intel/fsp2_0: Add new config option to support FSP CARpraveen hodagatta pranesh
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU microcode length and base address in CBFS to FSPT binary as init parameters. Add new config FSP_T_XIP in Kconfig, which is selected by platform config. If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup. Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01drivers/intel/wifi: Add DID for Intel WIFI module 8260, 8275Subrata Banik
Change-Id: I38d83370e96cff6822a96da5fa3d9af797ba1dc1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-16drivers/intel/gma: Fix OpRegion Mailbox3 synchronizationNico Huber
Make XBCM `Serialized` (obvious), and check for the callee clearing the request bit (we checked only the status for 0 which we potentially wrote ourselves). Change-Id: Ic92d525eda8d0a159fa5ddaacf230658d71c1578 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-16acpi: Call acpi_gen_writeSTA by status from device treeHung-Te Lin
The device tree now supports 'hidden' and the status can be found in `struct device.hidden`. A new acpi_device_status() will return the expected setting of STA from a `struct device`. BUG=b:72200466 BRANCH=eve TEST=Builds and boots properly on device eve Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28567 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14drivers/intel/gma: Do not rely on CBLV in OpRegion Mailbox3Nico Huber
CBLV is not kept up to date by Linux' i915. We should fix that too, but it will likely take some years until we can always expect it to work. For now read the register values directly. To accomodate that we are not the only one writing those, revise XBQC() to search for the closest value in BRIG (instead of a lower equal one) and round more accurately for better matches. Change-Id: I4e2d8fa34e75463d4cf7242af3e2c67577cfa2a5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-10complier.h: add __noreturn and use it in code baseAaron Durbin
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace current users with the macro. Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-06intel/fsp2_0: Add fsp2.1 shared stack feature supportAamir Bohra
FSP 2.1 implementation is adding features on top of fsp2_0. One such feature is a shared stack implementation that requires coreboot to allocate stack for fspm and then fsp uses the same stack as coreboot. This implementation adds support for shared stack feature. Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/28358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02drivers/intel/fsp1_1: Fix typoWim
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Change-Id: I9c6b063970fa328650de3f4402fe203305b5b760 Reviewed-on: https://review.coreboot.org/28373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30drivers/intel/gma: Fix OpRegion Mailbox3 backlight changeNico Huber
We should always update BCLP, no matter if the driver is ready yet to process the request. This way it will hold the current value when the driver initializes. Change-Id: I4b091d744f95da39abe542966f0a8589a187573b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30drivers/intel/gma: store uint8_t brightness values in mailbox3Alexander Couzens
The _BCM function requires a percentage value. While the brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%. Previous implementation stored the percentage brightness value resulting in limiting the brightness to ~40% of it's maximum power. Only affects brightness control using mailbox3. Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3") Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27drivers/intel/wifi: Make WIFI_SAR_CBFS user visibleFurquan Shaikh
This change makes WIFI_SAR_CBFS user selectable option so that it can be enabled/disabled from menuconfig along with the SAR filepath. BUG=b:112425861 Change-Id: Idf6feaefe68e7ebf6786c2c36e92a054fba4483c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14src: Remove duplicated 'include <device/device.h>'Elyes HAOUAS
Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-12drivers/intel/wifi: Get rid of unused wrdd.aslFurquan Shaikh
This change gets rid of unused wrdd.asl in intel wifi driver. This file became redundant when all boards moved to using SSDT for wifi device. Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27963 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12drivers/intel/wifi: Skip adding SSDT entry if device is disabledFurquan Shaikh
This change checks to ensure that device is enabled before adding entry into SSDT. BUG=b:112371978 Change-Id: Ibe4811bef8cf0978b7a82d66a32f96247b9c823d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10src/drivers: Fix typoElyes HAOUAS
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-04drvs/intel/gma/acpi: Add methods to use MBOX3Patrick Rudolph
* Add Mailbox 3 driver * Request brightness change through Mailbox 3 * Return Ones on error or if unsupported * Mark existing code as legacy (still required if no GMA driver is running) * Call legacy code if Mailbox 3 is unsupported, on error or if gma driver isn't running Tested on Lenovo T430: * Brightness control still works * Brightness is the same on S3 resume Change-Id: I51554c819148336b204d28972cbf775a10c3fb8a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19drivers/intel/gma: Default to LVDS for Internal on NEHALEMArthur Heymans
Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not support eDP, therefore default to LVDS. Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27512 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17security/vboot: Add interface for FSP 2.0 mrc cachingPhilipp Deppenwiese
* Move vboot/tpm specific implementation to vboot. * Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set. * Preparation for software hash function support, no logic changed. Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24904 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13intel/wifi: Add WGDS ACPI method for Geo Aware SARPratik Prajapati
To comply with all relevant bodies throughout the world, SAR settings take into account the lowest common denominator Tx power settings. This setup may lead to non-optimal performance when the user location is in a country that may allow higher power setting. The purpose of Wireless Geo Delta Settings (WGDS) is to provide offset settings for FCC, Europe, Japan and Rest of the world. These offsets would be added (by Intel wifi driver) to the base SAR Tx Power as defined in WRDS and EWRD BUG=b:65155728 BRANCH=none TEST=WGDS ACPI table gets created as expected. Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-09src/{device,drivers}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28drivers/intel/fsp2_0: Fix uncountable "information"Elyes HAOUAS
Change-Id: I91e13a786b12328f1d9200f76788faa19847bbe7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-27drivers/intel/fsp1_1: Fix vbt_len typeMatt DeVillier
Type of vbt_len should be size_t, change to fix compiler error Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-22drivers/fsp1_1: fix VBT Loading by using GMA common functionMatt DeVillier
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in CBFS, but only changed the loader in soc/intel/common, forgetting the separate one used by FSP 1.1. As the soc/intel/common loader has now been rolled into the one in drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one. Also, remove 2 now-unused header files. Test: build/boot google/chell, observe display initialized prior to OS load, no FSP warning in cbmem console due to invalid VBT signature. Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 14:22:37 +0000