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2019-05-14Remove unnecessary ENV_RAMSTAGE guardSubrata Banik
TEST=Able to build coreboot for CML. Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-30drivers/uart/oxpcie: Fix early consoleKyösti Mälkki
Fix build for POSTCAR_STAGE=y. Also add driver for bootblock and verstage. Change-Id: If57033353c07854e21b630c58ad69931eb572da9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-21(console,drivers/uart)/Kconfig: Fix dependenciesNico Huber
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-20drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IONico Huber
It defaults to y to avoid having to select it per mainboard. But that makes a mess because it results in linker conflicts unless other UART drivers disable it explicitly. We try to be smarter about the default value for now. The real solu- tion would be to hardcode it per mainboard. But who knows which boards actually have it? Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29571 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-13uart/sifive: make divisor configurablePhilipp Hug
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-06-08arch/x86: Drop leftover ROMCC console supportKyösti Mälkki
Change-Id: I3e52569a34e1f7bfea8be9da91348c364ab705e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-04drivers/uart/oxpcie.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27drivers/uart: Allow the 8250IO driver only on x86Jonathan Neuschäfer
The driver relies on I/O space access functions (inb, etc.), which are only available on x86. Rather than explicitly disallowing it on ARM, allow it only on x86. TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not available in the "Generic Drivers" menu anymore. Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26drivers/uart: Add helper function to allow bit-bangingJulius Werner
In some cases it may be useful to be able to bitbang a UART, such as during early bring-up when a driver for the actual controller isn't available yet. On some platforms we may even want to use this permanently, such as on the SDM845 where the hardware UART controller needs to have firmware loaded and is thus unavailable for most of the bootblock. This patch adds some helper code that makes it easy to implement this on a platform, you just have to pass it a function to control the Tx pin state and it will do the rest. It relies on the mono_time API and is thus bound to microsecond timing granularity, but that seems to be barely good enough for 115200 baud if the bit times are calculated carefully. Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25812 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25drivers/uart: Add a driver for SiFive's UARTJonathan Neuschäfer
This UART is used in the SiFive FU540 SoC, and will probably be used in other SoCs in the future. Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-13drivers/uart/pl011.c Add read supportMarcello Sylvester Bauer
Implement uart_rx_byte Change-Id: I5a33b3cd4b333fb244bc55747014a301021e25e0 Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/25623 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05src/drivers/pl011: Add verstage supportPatrick Rudolph
Build pl011 to support building vboot on arm platforms. Change-Id: I1ddc372d558b380065ff944fccb0d84eb37d4213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-13drivers/uart/pl011: Improve PL011 driverDavid Hendricks
This adds a struct for registers along with some bits from ATF to the generic PL011 driver. It also adds a naive implementation of uart_tx_flush() which was previously stubbed out. Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-16drivers/uart8250mem: Check for zero base addressMarshall Dawson
Before adding a new UART to the coreboot/lb table, verify that it has a non-zero base address. This is consistent with all other functions that use the uart_platform_base() function. This was tested on google/kahlee by using an invalid UART number and forcing the base address to 0. Execution was able to complete through depthcharge and into the OS. Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21996 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-04drivers/uart: Use baudrate of 115200 by defaultFurquan Shaikh
If TTYS0_BAUD is not configured, then by default use baudrate of 115200. BUG=b:64030366 Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13src/drivers: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-18uart: Fix bug in {uart8250, uart8250_mem, ns16550}_rx_byte functionsWerner Zeh
We have several different UART implementations of which three support a timeout when receiving characters. In all of these three implementations there is a bug where when the timeout is hit the last received character will be returned instead of the needed 0. The problem is that the timeout variable i is decremented after it has been checked in the while-loop. That leads to the fact that when the while-loop is aborted due to a timeout i will contain 0xffffffff and not 0. Thus in turn will fool the following if-statement leading to wrong return value to the caller in this case. Therefore the caller will see a received character event if there is none. Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-13drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.cNico Huber
And don't link it. It's for ROMCC. To make code happy that uses the ROMCC interface read_option(), read_option_lowlevel() is ported to mc146818rtc.c along with a message to use get_option() instead. Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-30drivers/uart/oxpcie_early.c: remove uart_fill_lb()Martin Roth
uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the Oxford OXPCIe952 Kconfig option is enabled, we were getting an error. "multiple definition of `uart_fill_lb'" The new version of uart_fill_lb sets the regwidth depending on the Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't give DRIVERS_UART_OXPCIE as a choice. Change-Id: Ife24ab390553b10b2266809595c2e06463de708c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-30Kconfig: Prefix hex defaults with 0xMartin Roth
Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16827 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30soc/intel/fsp_broadwell_de/uart: Drop itNico Huber
A copy of our uart8250io driver sneaked in with Broadwell-DE support. The only difference is the lack of initialization (due to FSP handling that). TEST=manually compared resulting object files Change-Id: I09be10b76c76c1306ad2c8db8fb07794dde1b0f2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16786 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31src/drivers: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16321 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-25drivers/uart: Enable debug serial output during postcarLee Leahy
Build the UART drivers for the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15843 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09drivers/uart: Enable override for input clock dividerLee Leahy
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21*/Makefile.inc: Compile files needed by uart8250 in x86 bootblockAlexandru Gagniuc
These files provide symbols needed by console and uart drivers. This was not an issue in the past, as we were not setting up a C environment this early in the boot process. Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-14x86: add standalone verstage supportAaron Durbin
To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-04drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabledAlexandru Gagniuc
Users of DRIVERS_UART_8250MEM_32 would have to also select DRIVERS_UART_8250MEM to avoid missing Kconfig dependencies. Instead, do what the OXPCIE driver dies and select the appropriate options. Change-Id: I40d93df024fcb3a9ad6dc51d6a5966e7b1b6c07f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11786 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-08-13uart8250mem: provide uart_fill_lb()Aaron Durbin
There was no implementation for uart_fill_lb() in the 8250mem driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are employed then the build doesn't fail. BUG=chrome-os-partner:43419 BRANCH=None TEST=Built with glados using 8250MEM Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289899 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I972b069a4def666f509268816de91ed6c0f655d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11169 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21console: Add UART8250MEM 32bit supportNaveen Krishna Chatradhi
This patch adds UART8250MEM_32 feature flag to support UART8250 compatible with 32bit access in memory mapped mode. [pg: rebuilt to reuse the existing UART8250 8bit access driver which reduces code duplication.] Change-Id: I310e70dfab81dcca575e9931e0ccf93af70efa40 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c3b2c628b854e8334540ff5158c2587dbfabf95 Original-Change-Id: I07ee256f25e48480372af9a9255bf487c331e51d Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-11secmon: Add some missing filesPatrick Georgi
secmon is referring to uart's default_baudrate() and various coreboot version strings. Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-07kbuild: Use wildcard for driver subdirectoriesStefan Reinauer
Change-Id: Id1685c0b28ec8e3ab972a671af6f2de6f321c645 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28OxPCIe: Fix UART base addressesKyösti Mälkki
The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-14OxPCIe952: Fix read8/write8 argumentKyösti Mälkki
This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-15uart8250mem: Add wrapper for MMIO register accessKyösti Mälkki
For some UART hardware registers are 32 bits wide, so we will need base_port + reg << 2 instead. Prepare for that change and unification of MMIO between ARM and x86. Change-Id: I5fa2c2f7ee4872499a01754c1ba872a8addf499c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7793 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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