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2021-03-15drivers/generic/alc1015: Change HID name for driverEric Lai
From ALSA reviewer suggest to change the name to RTL1015. Details in below threads: https://www.spinics.net/lists/alsa-devel/msg123395.html BUG=b:177971830 TEST=: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2762852bdc3164346e3618c373aa4d3336415653 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-15drivers/generic/alc1015: Fix missing _DSD and correct property nameEric Lai
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for driver. BUG=b:177971830 TEST: ALC1015P driver can get sdb-gpio properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11driver/intel/fsp2_0: Allow function to run serially on all APsAamir Bohra
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread which indicates whether the work should be scheduled in a serially on all APs or in parallel. Current implementation of this function mp_startup_all_aps always schedules work in parallel on all APs. This implementation ensures mp_startup_all_aps honors to run serialized request. BUG=b:169114674 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10drivers/i2c: sx9310: Replace register map with descriptive namesGwendal Grignou
The current driver is using chip registers map to configure the SAR sensor, which is opaque, especially when the datasheet is not published widely. Use more descriptive names, as defined in Linux kernel documentation at https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml BUG=b:173341604 BRANCH=volteer TEST=Dump all tables, check semtech property: for i in $(find /sys/firmware/acpi/tables/ -type f) ; do f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat done In SSDT.dsl, we have: Package (0x06) { Package (0x02) { "semtech,cs0-ground", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, Package (0x02) { "semtech,proxraw-strength", Zero }, Package (0x02) { "semtech,avg-pos-strength", 0x0200 }, Package (0x02) { "semtech,combined-sensors", Package (0x03) { Zero, One, 0x02 } }, Package (0x02) { "semtech,resolution", "finest" } } Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10drivers/usb/pci_xhci: Add cezanne xhci pci devce idMathew King
BUG=b:180529005 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I836bb838cc97593451f869490ff3c9dd156245b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51349 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08cbfs: Pull handling of the CBFS_CACHE mem_pool into CBFS coreJulius Werner
This patch pulls control of the memory pool serving allocations from the CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the CBFS API. Previously, platforms would independently instantiate this as part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache pool is exported as a global so these platforms can still use it to directly back rdev_mmap() on their boot device, but the cbfs_cache can now also use it to directly make allocations itself. This is used to allow transparent decompression support in cbfs_map(). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-05drivers/intel/gma/gma.ads: Uniformize casingAngel Pons
Use lowercase `port` in both the spec and the body. Change-Id: I3d1e2abe03eedcaf57716af444a3e3b8a61b60d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-04src/drivers/i2c/rx6110sa: Add official ACPI IDWerner Zeh
In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily) the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was removed. In the meantime Seiko-Epson did a great job and registered an official vendor ID in the ACPI database [1]. Further on, Seiko-Epson has now assigned the unique Product Identifier for the RX6110SA, which is '6110'. The assignment of the Product Identifier is controlled by the vendor and there is no official database where this ID is stored in. It is up to the vendor to make sure that this ID stays unique. This patch adds this new vendor and product ID to the driver. Together with a pending Linux patch this RTC is now useable as ACPI device in Linux. [1] https://uefi.org/ACPI_ID_List?search=SECC Change-Id: I45838162f014a760520692c6dcaae329ad98547d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176 Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04drivers/generic/max98357a: Use depends HAVE_ACPI_TABLESEric Lai
Replace if HAVE_ACPI_TABLES statement with depends HAVE_ACPI_TABLES. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie6ebfde49f0f3c205e174c5113feb75444dedba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04drivers/generic/alc1015: add ALC1015 AMP driverEric Lai
Add ALC1015 AMP support. ALC1015Q-VB Datasheet Rev 0.1 BUG=b:177971830 TEST: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51051 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01skylake,fsp1_1: Delete dead `report_memory_config()` functionAngel Pons
RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27drivers/soundwire/alc1308 : Add ALC1308 soundwire deviceAnil Kumar
This patch adds new soundwire device ALC1308 The codec properties are filled out as best as possible with the datasheet as a reference. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. The unique ID is calculated from schematics by referring to ASEL[1:0] strap settings. Datasheet of ALC1308 provides info about the mapping of ASEL strap settings to unique ID For example this device is connected to master link ID 1 and has strap settings configuring it for unique ID 2. chip drivers/soundwire/alc1308 register "desc" = ""Left Speaker"" device generic 1.2 on end end Bug=None Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for PCI0.HDAS.SNDW are present for ALC1308 Test speaker out functionality Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.hRonak Kanabar
From JSL FSP v2376 "FirmwareVersionInfo.h" header file is added and "FirmwareVersionInfoHob.h" is deprecated. This patch adds support to display firmware version information using "FirmwareVersionInfo.h" header file. Changes included in this patch: - Add Kconfig to select FirmwareVersionInfo.h - Add code change to display firmware version info using FirmwareVersionInfo.h header No change in version info print format. BUG=b:153038236 BRANCH=None TEST=Verify JSLRVP build with all the patch in relation chain and verify the version output prints no junk data observed. couple of lines from logs are as below. Display FSP Version Info HOB Reference Code - CPU = 8.7.16.10 uCode Version = 0.0.0.1 Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-02-23intel/fsp2_0: Fix the mp_get_processor_infoAamir Bohra
FSP expects mp_get_processor_info to give processor specfic apic ID, core(zero-indexed), package(zero-indexed) and thread(zero-indexed) info. This function is run from BSP for all logical processor, With current implementation the location information returned is incorrect per logical processor. Also the processor id returned does not correspond to the processor index, rather is returned only for the BSP. BUG=b:179113790 Change-Id: Ief8677e4830a765af61a0df9621ecaa372730fca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50880 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23drivers/intel/fsp2_0/memory_init: check if UPD struct has expected sizeFelix Held
If the UPD size in coreboot sizes mismatches the one from the FSP-M binary, we're running into trouble. If the expected size is smaller than the UPD size the FSP provides, call die(), since the target buffer isn't large enough so only the beginning of the UPD defaults from the FSP will get copied into the buffer. We ran into the issue in soc/amd/cezanne, where the UPD struct in coreboot was smaller than the one in the FSP, so the defaults didn't get completely copied. TEST=Mandolin still boots. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-20drivers/generic/bayhub_lv2: remove unnecessary configsVictor Ding
coreboot sets up CLK_PM, ASPM, and L1ss automatically based on related bits in "Link Capability Register" and "L1 PM Substates Capabilities Register". coreboot overrides these configs even if the driver sets them. Therefore, setting up CLK_PM, ASPM, and L1ss in the driver is redundant and useless. BUG=b:177955523 BRANCH=zork TEST="lspci -vvvv" prints are identical with and without this patch; LV2_LINK_CTRL(0x90) is 0x00110102 with and without this patch. Signed-off-by: Victor Ding <victording@google.com> Change-Id: I17c19f4271da426ac2b926b948378dc88131e95a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20drivers/generic/bayhub_lv2: move the driver to ".enable"Victor Ding
coreboot sets up certain configs (e.g. L1ss) based on the device's reported capacities; however, this BayHub lv2 driver modifies some of its capacities after coreboot uses them. Therefore, coreboot may make incorrect configs based on out-of-date capacities. This patch moves the driver from ".init" to ".enable" so that the capacities are set before the rest of coreboot queries them. BUG=b:177955523 BRANCH=zork TEST="lspci -vvvv" reported "PCI-PM_L1.2-" and "ASPM_L1.2-" on L1SubCtl1 of both PCI device "00:01.3" and "02.00.0" Signed-off-by: Victor Ding <victording@google.com> Change-Id: I857b7c7c6732bbd26de561052affa3a3e7e25737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18drivers/i2c/hid: Enforce level triggered IRQ modeKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. This change ensures that the IRQ is appropriately configured. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild. Build and boot to OS in Dedede. Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-17drivers/intel/fsp2_0: Allow larger FSPS UPD than expected in corebootNikolai Vyssotski
Enforcing the exact match of FSPS UPD block size between FSP and coreboot mandates simultaneous updates to coreboot and FSP repos. Allow coreboot to proceed if its UPD structure is smaller than FSP one. This usually indicates that FSPS has an updated (larger) UPD structure which should be soon matched/updated on the coreboot side to keep them in sync. While this is an undesirable situation that should be corrected ASAP, it is safe from coreboot perspective. It is safe (as long as default values in FSP UPD are sane enough to boot) because FSPS UPD buffer is allocated on the heap with the size specified in FSPS (larger) and filled with FSPS default values. This allows FSP UPD changes to be submitted first followed by changes in coreboot repo. Note that this only applies to the case when entire FSPS UPD structure grows which should be rare as FSP should allocate enough reserve space, anticipating future expansion, to keep the structure from growing when new members are added. BUG=b:171234996 BRANCH=Zork TEST=build Trembyle Change-Id: I557fd3a1f208b5b444ccf76e1552e74ecf4decad Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-16src/{drivers,security}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Ief86a596b036487a17f98469c04faa2f8f929cfc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15src/drivers: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I38d565f82d078cb75f74f8502fcafdedd907b97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50523 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15drivers/spi: Stop using a variable-length arrayAngel Pons
Only the call in `spi_flash_cmd_write_page_program` uses non-constant values for the array length. However, the value for `data_len` has an upper bound: `flash->page_size` is set to `1U << vi->page_size_shift` which depends on the flash chip vendor info, and the largest value it can currently have is 8. Thus, the maximum page size is currently 256. Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on the amount of data that can be written in one command. Then, use this value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also, add a check to prevent buffer overflow problems. Finally, ensure that the `spi_flash_cmd_write_page_program` function always writes no more than 256 bytes of data when using the `spi_flash_cmd_write` function. Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works. Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-10src: Remove unused <boot_device.h>Elyes HAOUAS
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07src: Remove redundant <commonlib/bsd/compiler.h>Elyes HAOUAS
Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07src: Remove redundant include <rules.h>Elyes HAOUAS
Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04drivers/generic/bayhub_lv2: Add driver for BayHub lv2John Su
Add a driver which puts the device into power-saving mode. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03drivers/aspeed: Fix some issuesPatrick Rudolph
* Use probe_resource instead of find_resource. This prevents a call to die and instead returns NULL. * Handle the case where BAR2 isn't present * Don't hardcode legacy VGA when BAR2 is present. This fixes graphic initialisation when the Aspeed isn't the primary GPU and thus doesn't decode VGA cycles. This makes the coreboot code more similar to the Linux kernel code. Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01bayhub bh720: Add helpers to access PCR registersAngel Pons
The BH720 PCR registers are accessed using an index/data register pair. Introduce some helper functions to clarify the PCR register operations. Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-01ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocpJohnny Lin
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-01drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CARArthur Heymans
TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans
Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30drivers/intel/fsp2_0: factor out and improve UPD signature checkFelix Held
In case of a mismatch print both the UPD signature in the FSP and the expected signature and then calls die(), since it shouldn't try calling into the wrong FSP binary for the platform. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-29stage_cache: Add resume_from_stage_cache()Kyösti Mälkki
Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29drivers/intel/fsp1_1: Drop s3_resume parameter to load_vbt()Kyösti Mälkki
Change-Id: Iaba88026906132b96fe3db3f05950df0e7eef896 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29intel/fsp1_1: Declare fsp_load() as staticKyösti Mälkki
The function has only one local call-site. Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28bayhub bh720: Factor out common HS200 init codeAngel Pons
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28drivers/elog: Correct code styleFrans Hendriks
lint report errors Solve the POINTER_LOCATION errors BUG = N/A TEST = N/A Change-Id: I65926abd6bbaff1efce39efad9ec92c4f364b533 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49971 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Rename __protected_start symbolKyösti Mälkki
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25drivers/intel/fsp2_0/header_display.c: Correct component_attribute checkBenjamin Doron
According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2, BIT1 indicates an "official" build. Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25bayhub bh720: Configure VIH tuning via devicetreeAngel Pons
There's no need to repeat the same code on every board. Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24drivers/intel/gma/opregion.c: Use __func__Elyes HAOUAS
Change-Id: Ia45825ade0c9d24d5b87882e21bfc6df82a693e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24drivers/elog/elog.c: Use __func__Elyes HAOUAS
Change-Id: I024a0c2d7c53634c58d5d80522933ecad554d7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 09:38:24 +0000