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2020-07-28drivers/i2c/max98373: fix error message formattingCaveh Jalali
This adds a missing newline to a printk in the max98373 driver. BUG=none TEST=verified BIOS boot log is properly formatted on volteer. Change-Id: I1c989729bdc71736975901566023e0057a6d0556 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28drivers/wifi: Adapt generic wifi driver into a chip driverKarthikeyan Ramasubramanian
Re-organize the existing generic wifi driver into a generic wifi chip driver. This allows generic wifi chip information to be added to the devicetree. BUG=None TEST=./util/abuild/abuild Change-Id: I63f957a008ecf4a6a810c2a135ed62ea81a79fe0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28Revert "src: Remove unused include <cpu/x86/smm.h>"Patrick Rudolph
This reverts commit 6f739184dd153e0f7c3fa42990e008578b51b2c1. Fixes compiling the SMMSTORE driver. Change-Id: I3b4d4063ded50529bea48f8d865c1689fe9e26d1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src/drivers/intel/soundwire/soundwire.h: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: Icf8b77713e7b5deb9def19c3e14e89a40ba46107 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26drivers/intel/dptf: Remove prompts from DPTF config optionsTim Wawrzynczak
The prompts for the DPTF Kconfig options were not necessary, they should be selected based on what DPTF implementation is being used, ASL files or generated at runtime. It's not really meant to be fiddled with at build-time. Also rewrite the help text for the _HID selection, to try and make it more clear when to use y or n. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6edcabd28426916d9586d501b95b510dfc163fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43830 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26drivers/mrc_cache: Avoid unused variable assignmentPaul Menzel
Fix the scan-build warning below: CC romstage/drivers/mrc_cache/mrc_cache.o src/drivers/mrc_cache/mrc_cache.c:450:26: warning: Value stored to 'flash' during its initialization is never read const struct spi_flash *flash = boot_device_spi_flash(); ^~~~~ ~~~~~~~~~~~~~~~~~~~~~~~ 1 warning generated. The function can return early before the value is read. Fix this, by getting rid of the variable, as the value is only read once. Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09 Found-by: scan-build (clang-tools-9 1:9.0.1-12) Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
BOOL type Kconfig values should be used through the CONFIG() macro. These instances were not, so update them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26drivers/usb: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1430454 TEST=Built and boot up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I8ece3831bbd2641ceafbd71b9dc3db7e04a8eae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43449 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26drivers/intel/dptf: Add missing Scope operator for _FIFTim Wawrzynczak
Missed one other scope operator in the DPTF cleanup. This one is for the fan device, and without this fix, the kernel isn't able to properly control the fan (it gets confused about whether it's ACPI 4+ compatible or not). BUG=b:149722146 TEST=verify /sys/class/thermal/cooling_zone0/max_state returns > 1, and /sys/class/thermal/cooling_zone0/cur_state is writable, and writing the value of `max_state` causes the fan to spin faster. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7bd83967ace761ddd17eaeae9c25abb0b2cbe413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Remove unused include <cpu/x86/smm.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/smm.h>' -- src/) <(git grep -l 'SMM_DEFAULT_BASE\|SMM_DEFAULT_SIZE\|SMM_BASE\|SMM_ENTRY_OFFSET\|SMM_SAVE_STATE_BEGIN\|APM_CNT\|APM_STS\|apm_control\|set_smm_gnvs_ptr\|set_acpi_mode_on_exit\|io_trap_handler\|southbridge_io_trap_handler\|mainboard_io_trap_handler\|southbridge_smi_set_eos\|smm_southbridge_clear_state\|global_smi_enable\|global_smi_enable_no_pwrbtn\|cpu_smi_handler\|northbridge_smi_handler\|southbridge_smi_handler\|mainboard_smi_gpi\|mainboard_smi_apmc\|mainboard_smi_sleep\|smramc_dev\|smramc_reg\|run_smm_relocate\|smm_is_really_enabled\|is_smm_enabled\|smram_open\|smram_close\|smram_lock\|smm_open\|smm_close\|smm_lock\|_binary_smm_start\|_binary_smm_end\|smm_runtime\|smm_module_params\|smm_handler_start\|smm_get_save_state\|smm_handler_t\|smm_loader_params\|smm_setup_relocation_handler\|smm_load_module\|backup_default_smm_area\|restore_default_smm_area\|smm_region\|SMM_SUBREGION_HANDLER\|SMM_SUBREGION_CACHE\|SMM_SUBREGION_CHIPSET\|SMM_SUBREGION_NUM\|smm_subregion\|smm_list_regions' -- src/)|grep '<' Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-20drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring strapsAngel Pons
Unconditionally selecting `GFX_GMA_IGNORE_PRESENCE_STRAPS` creates a hard dependency on `MAINBOARD_USE_LIBGFXINIT`, which is undesired. Move it out of the `if GFX_GMA` block to break this unwanted dependency. TEST=Build for Librem 13v4 with no graphics init successfully. Change-Id: I53e132c209c065068f20959fa1a6f5195f5fe766 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-18drivers/intel/dptf: Add missing scope operator around TSR optionsTim Wawrzynczak
The previous DPTF patch train missed the proper scope operator around all of the TSR options. Without this, the optional GTSH and/or _STR Methods end up in the wrong scope. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18dptf: Fix scope of TCPU deviceTim Wawrzynczak
In the initial DPTF refactor, the scope of the TCPU device was incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the way that the acpi_inject_dsdt() callback currently works (it injects contents before the dsdt.aml file), the Scope where the TCPU device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing games with *when* things are defined in the DSDT, switch to defining all of the DPTF devices in the SSDT. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17drivers/amd/i2s_machine_dev: Add a driver for AMD I2S machine deviceFurquan Shaikh
This change adds a new driver for AMD I2S machine device. Currently, this device is added as part of `acp_fill_ssdt()` in Picasso, but with addition of this driver, this device can be added just like any other device in the devicetree. BUG=b:157708581 Change-Id: I49d1a867d7941397acca1054632b6ad855a021de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14src: Drop unused <cpu/x86/tsc.h> includeElyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<' Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src/drivers/usb/gadget.c: Add missing includeElyes HAOUAS
Replace unused <stddef.h> with missing <stdint.h>. Change-Id: I1ca111a30153526c3915bf393208fb2b4c569c01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43347 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src/drivers/usb/ehci_debug.c: Add missing includeElyes HAOUAS
Replace unused <stddef.h> with missing <stdint.h>. This is needed for 'u64'. Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/volteer: Convert static ASL files to new DPTF implementationTim Wawrzynczak
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12drivers/usb/pci_xhci: Don't return ACPI names for missing portsRaul E Rangel
We only want to return an ACPI name for a USB port if the controller physically has the port. This has the desired side effect of making the usb_acpi driver skip generating an ACPI node for a device which has no port. This prevents writing an invalid SSDT table which the OS then complains about. BUG=b:154756391, b:158096224 TEST=Boot picasso trembyle and verify HS05, HS06 and SS05 are no longer generated. Also checked the logs and saw the devices being ignored. \_SB.PCI0.LPCB.EC0.CREC.TUN0: Cros EC I2C Tunnel at GENERIC: 0.0 \_SB.PCI0.LPCB.EC0.CREC.MSTH: Cros EC I2C Tunnel at GENERIC: 1.0 \_SB.PCI0.LPCB.EC0.CREC.ECA0: Cros EC audio codec at GENERIC: 0.0 \_SB.PCI0.PBRA.XHC0.RHUB.HS01: Left Type-C Port at USB2 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.HS02: Left Type-A Port at USB2 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.HS03: Right Type-A Port at USB2 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.HS04: Right Type-C Port at USB2 port 3 xhci_acpi_name: USB2 port 4 does not exist on xHC PCI: 03:00.3 xhci_acpi_name: USB2 port 5 does not exist on xHC PCI: 03:00.3 \_SB.PCI0.PBRA.XHC0.RHUB.SS01: Left Type-C Port at USB3 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.SS02: Left Type-A Port at USB3 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.SS03: Right Type-A Port at USB3 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.SS04: Right Type-C Port at USB3 port 3 xhci_acpi_name: USB3 port 4 does not exist on xHC PCI: 03:00.3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia645380bea74f39fd94e2f9cbca3fcd4d18a878e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12drivers/usb/pci_xhci: Switch to using xhci_for_each_supported_usb_capRaul E Rangel
This removes some boilerplate code. BUG=b:154756391 TEST=Dump ACPI table for trembyle and verify it didn't change. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idcda4356f4e6cb7f6066c67e8fabe0299a1a75b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11drivers/usb/ehci_debug.c: Drop preprocessor usageAngel Pons
There's no need to use ugly preprocessor here when regular C conditional statements will work just fine. Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-11arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11drivers/i2c/w83793: Drop dead codeAngel Pons
Nothing selects this driver. Drop it before it grows moss. Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43268 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10drivers/usb/pci_xhci: Add Picasso xHCI controllersRaul E Rangel
BUG=b:154756391 TEST=Dump ACPI table and see xHCI nodes being created. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1541dc8ebf314a204708a7767f30f4db72990907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43331 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10drivers/usb/pci_xhci: Add a driver to generate xHCI ACPI nodesRaul E Rangel
We can use xhci_for_each_ext_cap to inspect the xHC so we generate the correct number of device nodes. Scope (\_SB.PCI0.PBRA) { Device (XHC1) { Name (_ADR, 0x0000000000000004) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x1F, 0x03 }) Device (RHUB) { Name (_ADR, Zero) // _ADR: Address Device (HS01) { Name (_ADR, 0x01) // _ADR: Address } Device (HS02) { Name (_ADR, 0x02) // _ADR: Address } Device (SS01) { Name (_ADR, 0x03) // _ADR: Address } } Name (_S0W, Zero) // _S0W: S0 Device Wake State Name (_S3W, 0x04) // _S3W: S3 Device Wake State Name (_S4W, 0x04) // _S4W: S4 Device Wake State } } BUG=b:154756391 TEST=Boot trembyle and look at ACPI table. See all xHCI nodes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41900 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09drivers/i2c/adt7463: Drop dead codeAngel Pons
Nothing selects this driver. Drop it before it grows moss. Change-Id: I9311dd07b8259384badec65da649fa0cf2da1e01 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43267 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09drivers/generic/generic: Drop dead codeAngel Pons
Nothing selects this driver. Drop it before it grows moss. Change-Id: I7f06ea45f90d502053c52ea0b7cd7aa6d52295c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43266 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09drivers/usb/ehci_debug.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-09drivers/dec/21143: Drop dead codeAngel Pons
Nothing is selecting this driver. Drop it before it grows moss. Change-Id: I9e2ba205154a9b37455c522721f5eb2ef9d76b40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09drivers/ti/tps65090: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Iebd9080cd0e859dce5e6c5398429c38d1aa075dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09drivers/intel/gma/i915_reg.h: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Iff5007256fedebd98082a575773d7de181b321ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09drivers/pc80/pc/i8259c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-07dptf: Add support for IDSPTim Wawrzynczak
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan and TSR optionsTim Wawrzynczak
DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Running Average Power LimitsTim Wawrzynczak
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2. BUG=b:143539650 TEST=compiles Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan Performance StatesTim Wawrzynczak
This change adds support for generating the _FPS table for the DPTF Fan object. The table describes different levels of fan activity that may be applied to the system in order to actively cool it. The information includes fan speed at a (rough) percentage level, fan speed in RPM, potential noise level in centibels, and power in mA. BUG=b:143539650 TEST=compiles Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Charger Performance StatesTim Wawrzynczak
This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Critical PoliciesTim Wawrzynczak
This patch adds support for DPTF Critical Policies, which are consist of Method definitions only. They are `_CRT` and `_HOT`, which are defined as temperature thresholds that, when exceeded, will execute a graceful suspend or a graceful shutdown, respectively. BUG=b:143539650 TEST=compiles Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Passive PoliciesTim Wawrzynczak
This patch adds support for emitting the Thermal Relationship Table, as well as _PSV Methods, which together form the basis for DPTF Passive Policies. BUG=b:143539650 TEST=compiles Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for generation of Active PoliciesTim Wawrzynczak
This change adds support for generating the different pieces of DPTF Active Policies. This includes the Active Relationship Table, in addition to _ACx methods. BUG=b:143539650 TEST=compiles Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07drivers/intel/dptf: Add current participant Devices to DSDTTim Wawrzynczak
In this DPTF implementation, the participant device objects are written into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID, PTYP, and _STR). All other Methods & Names will be written into the SSDT. If a device is not used in any policy, then its _STA is set to return 0 ("off"). BUG=b:143539650 TEST=Compiles. Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07drivers/intel/mipi_camera: Add camera power resource to SSDTSugnan Prabhu S
This change adds support function to parse entries in the devicetree to generate PowerResource entries for the MIPI camera. Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add support to handle CIO2 deviceMatt Delco
This change updates mipi_camera driver to handle CIO2 device type. Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42470 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: SSDT changes to add PLDMatt Delco
This change updates mipi_camera driver to add PLD section to SSDT. Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42469 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 08:46:55 +0000