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2017-05-03drivers/{aspeed,xgi_z9s}/Kconfig: Don't override NATIVE_VGA_USE_EDIDArthur Heymans
device is run before drivers to generate .config and the first default takes precedence so this override achieves nothing. Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03lib/edid.c: Differentiate between absent and non-conformant EDIDArthur Heymans
Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-28drivers/intel/fsp2_0: add option to incorporate platform memory versionAaron Durbin
On Chrome OS systems a memory setting change is needed to be deployed without updating the FSP blob proper. Under such conditions one needs to trigger retrain of the memory. For ease of use provide an option, FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC and mainboard memory setting version number into the FSP version passed to the platform. The lower 8 bits of the FSP version are the build number which in practice is normally 0. Use those 8 bits to include the SoC and mainboard memory settings version. When FSP, SoC, or mainboard memory setting number is bumped a retrain will be triggered. BUG=b:37687843 Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19452 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25drivers/storage: Add SD/MMC/eMMC driver based upon depthchargeLee Leahy
The SD/MMC support is broken into several pieces. There are three main data structures: * sdhci_ctrlr - This is SDHCI controller specific and defined in include/device/sdhci.h * sd_mmc_ctrlr - This contains generic controller management data and defined in include/device/sd_mmc_ctrlr.h * storage_media - This contains the flash storage device management data and is defined in include/device/storage.h The SD/MMC driver consists of several components: * SDHCI controller code * bouncebuf.c * bouncebuf.h * pci_sdhci.c * sdhci.c * sdhci.h * sdhci_adma.c * sdhci_display.c * Flash storage device support * mmc.c * mmc.h * sd.c * sd_mmc.c * sd_mmc.h * storage.c * storage.h * storage_erase.c * storage_write.c Kconfig values enable various portions of the controller and storage drivers to be built to reduce the overall size of what is included in the final image. Full read/write/erase operations are provided for those platforms which want to take advantage. It is also possible to build the driver to perform initialization only. By default, this driver is not included in any platform, platforms must specifically select DRIVERS_STORAGE to add the SD/MMC support. After this patch is reviewed and merged, there are some additional patches: * Common CAR storage area - Use a predefined region of CAR to pass data structures between bootblock through to romstage. This allows early stages to preform the SD/MMC device initialization and later stages to use the SD/MMC device without further initialization. The example code initializes the SD/MMC device in bootblock and uses the SD/MMC device in romstage without further initialization. * CBMEM ID - Add a CBMEM ID value for the data structures so that they may be passed from romstage to ramstage and eventually the payload. The example uses the SD/MMC device in ramstage without further initialization. * Move the SD/MMC driver into commonlib * Have libpayload build the SD/MMC driver from commonlib. The intent is to pass the controller state to libpayload so that the SD/MMC device can be used without further initialization. * On some platforms, have depthcharge use the commonlib SD/MMC driver History: Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot and make the following changes: * Removed #include "config.h" from mmc.c, allow the lint tests to pass. * Move include files from drivers/storage into include/device. * Rename mmc.h to storage.h. * Add the Kconfig and Makefile and make edits to get the code to build. * Add support to initialize a PCI controller. * Fix formatting issues detected by checkpatch. * Fix data flow issues detected by checkpatch. * Add the missing voltage (MMC_VDD_35_36) into the voltage mask. * Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*. * Replace printf with sd_mmc_error. * Add sdhc_debug, sdhc_trace and sd_error macros. * Add Kconfig values to enable storage device debugging and tracing. * Add tracing and debug support to the SDHCI driver. * Allow SOC to override more controller features. * Split out ADMA support. * Move 1V8 support into SOC routine. * Move HS400 support into SOC routine. * Rework clock handling. * Change all controller references to use ctrlr. * Update the voltage handling. * Update modes of operation. * Move DMA fields into MmcCtrlr. * Update bus width support. * Change MMC_TIMING_* to BUS_TIMING_*. * Rename MMC_MODE_ to DRVR_CAP. * Move quirks into ctrlr->caps. * Associate removeable with the controller. * Statically allocate MmcMedia. * Replace the SdhciHost structure with the MmcCtrlr structure. * Split the code to support other SD/MMC controllers. * Split out erase and write support. * Update the code to be more consistent with the coreboot coding style. * Only expose calling APIs. * Divide up mmc.c into 4 modules: MMC, SD, storage card, common code. * Update debug and error messages. * Add partition support. * Display clock frequencies once in MHz. * Remove mmc_send_cmd, use ctrlr->send_cmd instead. * Handle error from sd_send_op_cond. * Allow mainboard to control delays around CMD 0. * Support command logging. * Mainboard may set delay after SD/MMC command. * Display serial number with sd_mmc_trace. * Remove cmd set parameter from mmc_switch. * Display errors for timeout and comm errors. * Add LED support. * Move 64bit DMA flag into ctrlr->caps. * Rework PIO transfer routine. * Add HS200 bus tuning. * Add support for HS400. * Use same format for HS400, HS200 and HS52. * Reduce storage_media structure size * Add routine to update code pointers * Add display of storage setup * Display controller setup TEST=Build and run on Reef and Galileo Gen2 Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19208 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-24drivers/i2c/tpm: Remove vendor.irqDaniel Kurtz
The vendor.irq field was originally intended for use as the TPM 1.2 "command complete" interrupt. However, all actual coreboot tpm drivers and hardware use the vendor.status method of checking command completion instead, and this irq field is not used. Let's just remove this unused functionality to simplify the code. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19396 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24drivers/i2c/tpm/cr50: Use tis_plat_irq_status for Cr50 IRQ statusDaniel Kurtz
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking the reception of commands. Real IRQs are not supported in firmware, however firmware can still poll interrupt status registers for the same effect. Commit 94cc485338a3 ("drivers/i2c/tpm/cr50: Support interrupts for status") added support for the Cr50 driver on X86 platforms to use a KConfig file to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is not supplied, the Cr50 driver inserts a 20 ms wait. Unfortunately this doesn't work so well when using the i2c connected Cr50 on ARM platforms. Luckily, a more generic implementation to allow a mainboard to supply a Cr50 IRQ status polling function was solved for SPI connected Cr50s by commit 19e3d335bddb ("drivers/spi/tpm: using tpm irq to sync tpm transaction"). Let's refactor the i2c c50 driver to use this same approach, and change eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for specifying the TPM flow control interrupt. This essentially reverts these two commits: 48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe 94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status And ports this commit to i2c/tpm/cr50: 19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction As a side effect the tpm_vendor_specific IRQ field goes back to its original usage as the "TPM 1.2 command complete" interrupt, instead of being repurposed to hold the flow control IRQ. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19363 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24drivers/spi/tpm: Do not let MAINBOARD_HAS_SPI_TPM_CR50 depend on SPI_TPMDaniel Kurtz
MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM is only on if we actually want to compile in the TPM code. For example, in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't depend on SPI_TPM. This problem manifests itself as the following build issue when building with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2": src/Kconfig:296:error: recursive dependency detected! src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50 src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50 src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2 src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2 MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Suggested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19411 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-24drivers/spi/spiconsole: Fix broken spiconsole driverFurquan Shaikh
Use spi_setup_slave to fill up the spi_slave structure with pointer to spi_ctrlr structure which can then be used to perform all spi operations. Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-24drivers/i2c/tpm: Hide ACPI on unsupported platformsPatrick Rudolph
Depend on I2C_TPM to prevent showing the menu entry on systems that do not have an I2C TPM installed. Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generatorV Sowmya
Add SSDT generator for MIPI CSI camera to create ACPI objects used by the Intel kernel drivers. * SSDB: Sensor specific database for camera sensor. * PWDB: Power database for all the camera devices. * CAMD: ACPI object to specify the camera device type. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated SSDT table has the required entries. Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18967 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-04-19elog: Print timestamp when logging eventJulius Werner
We're already reading the RTC whenever we file an event, we might as well print out the value at that time. Having a few RTC timestamps in the firmware log makes it easier to correlate that part of the log to a particular boot once we start having multiple boots in the log. Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13drivers/spi/tpm: Clean up SPI TPM driverFurquan Shaikh
1. Move common TIS macros to include/tpm.h. 2. Use common TIS macros while referring to status and access registers. 3. Add a new function claim_locality to properly check for required access bits and claim locality 0. BUG=b:36873582 Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19213 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-09drivers/spi: Get rid of spi_get_configFurquan Shaikh
There is only one user for spi_get_config i.e. SPI ACPI. Also, the values provided by spi_get_config are constant for now. Thus, get rid of the spi_get_config call and fill in these constant values in SPI ACPI code itself. If there is a need in the future to change these, appropriate device-tree configs can be added. BUG=b:36873582 Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-05drivers/spi/tpm: Allow TPM_SPI to be used with PC80_SYSTEM.Furquan Shaikh
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used with PC80_SYSTEM. BUG=b:35583330 Change-Id: Ibe626a192d45cf2624368db42d369202a4003123 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19093 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: Make SPI TPM driver CAR-safeFurquan Shaikh
1. Use proper CAR semantics for global/static variables. 2. Use spi_* functions directly instead of using a global structure to store pointers to those functions. BUG=b:36873582 Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: using tpm irq to sync tpm transactionJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/452284 Commit-Ready: Caesar Wang <wxt@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19113 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: try to wake cr50 if it is asleepJeffy Chen
BUG=b:35775002 TEST=boot from bob Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/452283 Commit-Ready: Caesar Wang <wxt@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-05drivers/spi/tpm: Add tis.c and tpm.c to ramstage and romstageFurquan Shaikh
These files are required to support recovery MRC cache hash save/restore in romtage/ramstage. BUG=b:35583330 Change-Id: Idd0a4ee1c5f8f861caf40d841053b83a9d7aaef8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-03drivers/i2c/tpm: remove 1260 byte buffer from stackAaron Durbin
The tis.c module is needlessly copying data to/from a 1260 byte buffer on the stack. Each device's transport implementation (cr50.c or tpm.c) maintains its own buffer, if needed, for framing purposes. Therefore, remove the duplicated buffer. BUG=b:36598499 Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19061 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/i2c/tpm: remove unused variable in tpm_transmit()Aaron Durbin
The 'ordinal' variable is not used. Remove it. BUG=b:36598499 Change-Id: I015a6633c0951980658b3c879e48bc84d604d62e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19060 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-03drivers/i2c/tpm: remove unused types from tpm.hAaron Durbin
There are unused structures/types in the tpm.h header file. Remove them. BUG=b:36598499 Change-Id: Iddc147640dcec70e80791846eb46298de1070672 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19059 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: honor tis_sendrecv() APIAaron Durbin
The spi tis_sendrecv() implementation was always returning success for all transactions. Correct this by returning -1 on error when tpm2_process_command() returns 0 since that's its current failure return code. BUG=b:36598499 Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19058 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: make tpm_info object local to compilation unitAaron Durbin
The tpm_info object is a global, but its symbol does not need to be exposed to the world as its only used within tpm.c. BUG=b:36598499 Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19057 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: de-assert chip select on transaction errorAaron Durbin
In the case of start_transaction() failing the chip select is never deasserted. Correct that by deasserting the chip select when start_transaction() fails. BUG=b:36598499 Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19056 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18903 Tested-by: build bot (Jenkins) Tested-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-31drivers/intel/gma: Guard GFX_GMA_* configsNico Huber
It's confusing to have these Kconfig symbols for non-Intel boards. Change-Id: I4903c816258e5d2b8ed8704295b777aee175e8bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18795 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-18nb/i945/gma.c: Refactor panel setupArthur Heymans
This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-17drivers/intel/fsp1_1: Fix issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" WARNING: line over 80 characters WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: suspect code indent for conditional statements (16, 32) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18886 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-16i2c/generic: Add support for GPIO IRQDuncan Laurie
Add support for using GPIO IRQ instead of PIRQ with an I2C device. This allows a device to use an edge triggered interrupt that will trigger on both high and low transitions. The _DSD method for describing these GPIOs has a field for 'active low' which is supposed to be 1 if the pin is active low, otherwise is zero. The value in here doesn't mean too much for GpioInt() as those will end up using the value from GpioInt() when it actually requests the interrupt. BUG=b:35581264 BRANCH=none TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18835 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16drivers/i2c/tpm: Add support for Atmel TPM (AT97SC3204)Lee Leahy
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the existing I2C TPM support. The Atmel part just passes the commands and responses from the TIS layer across the I2C interface. TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16drivers/i2c/tpm: Add TPM (TIS) debugging supportLee Leahy
Add debugging support for the TIS transactions for the I2C TPM chips. TEST=Build and run on reef Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15drivers/i2c/tpm: Fix issues detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: braces {} are not necessary for single statement blocks WARNING: Unnecessary parentheses - maybe == should be = ? WARNING: line over 80 characters WARNING: missing space after return type TEST=Build and run on Galileo Gen2 Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18832 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14drivers/intel/fsp1_1: Only display MMCONF address if supportedLee Leahy
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported. TEST=Build and run on Galileo Gen2 Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18801 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Switch from binary to decimalLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Avoid gcc v4.3+ binary constant extension: TEST=Build and run on Galileo Gen2 Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18747 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18746 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Remove braces for single statementsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space prohibited before open square bracket '[' ERROR: spaces required around that ':' (ctx:VxE) TEST=Build and run on Galileo Gen2 Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18744 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Add space before *Lee Leahy
Fix the following error detected by checkpatch.pl: ERROR: "(foo*)" should be "(foo *)" False positives are generated by checkpatch for the following condition which is not properly detecting the variable type: ERROR: need consistent spacing around '*' (ctx:WxV) The false positives are found in debug.h and upd_display.c TEST=Build and run on Galileo Gen2 Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Use tabs for indentLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: please, no spaces at the start of a line TEST=Build and run on Galileo Gen2 Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09drivers/spi/tpm: provide Kconfig to indicate CR50 usageAaron Durbin
Going forward it's important to note when a CR50 is expected to be present in the system. Additionally, this Kconfig addition provides symmetry with the equivalent i2c Kconfig option. BUG=b:35775104 Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp loadFurquan Shaikh
Add a function to allow FSP component loading separately from silicon initialization. This enables SoCs that might not have stage cache available during silicon initialization to load/save components from/to stage cache before it is relocated or destroyed. BUG=chrome-os-partner:63114 BRANCH=None TEST=Compiles successfully. Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18413 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20src/drivers/pc80: Update vga_font_8x16.c to be non-binaryMartin Roth
Previously, the file -i command identified vga_font_8x16.c as application/octet-stream; charset=binary Now it identifies as: text/x-c; charset=us-ascii - Remove non-ascii characters Change-Id: I6b513e6457a31828a6e94c954a7e2e7ee18fd4d6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18372 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-19drivers/spi/acpi: Add additional generic ACPI supportDuncan Laurie
Add support for more ACPI features in the generic SPI ACPI driver so it can be flexible enough to support more devices, or devices in different configurations. - add a wake pin - add support for using IRQ GPIO instead of PIRQ - add power resource support with enable and reset gpios BUG=chrome-os-partner:61233 TEST=ensure existing SSDT generation is unchanged, and test that new features generate expected code Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18393 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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