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2016-06-09soc/intel/apollolake: Update FSP header filesBora Guvendik
Update autogenerated FSP 2.0 generic header files based on FSP release 136_30. Changes were made to avoid duplicating some of the structs for every SoC. BUG=chrome-os-partner:50765 TEST=Build coreboot Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7145 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7584 Reviewed-on: https://review.coreboot.org/15081 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h headerAlexandru Gagniuc
Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03drivers/intel/fsp1_1: Make weak routines quietLee Leahy
Now that there is a better way of finding optional routines, make the weak routines quiet so that it may be used for the optional implementation. TEST=Build and run on Galileo Gen2 Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03Add Board Checklist SupportLee Leahy
Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02drivers/intel/fsp1_1: Update weak MRC cache routinesLee Leahy
Update the weak functions for the MRC cache. TEST=Build and run on Galileo Gen2 Change-Id: I54a1252cfff1a2f68b163f0feb65e2bceb37f6a9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15042 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02generic: Add a Maxim 98357A codec driverDuncan Laurie
The Maxim Integrated 98357A codec is an I2S slave device that has no control channel for configuration and instead provides a GPIO that is used for channel selection and power down. This means it does not fit into a bus hierarchy easily and is instead represented as a generic device and found with a static bus scan using the devicetree. This driver provides configuration options for passing the "sdmode" GPIO descriptor as well as a second option for "sdmode delay" which can configure the timing of the sdmode toggling in relation to the I2S channel output. In addition an GPIO can be provided to indicate to the driver whether this device is present or not. This can be used for board designs that may have different codec possibilities that are selected by HW strap. Sample usage for this device driver: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)" register "sdmode_delay" = "100" device generic 0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.HDAS) { Device (MAXM) { Name (_HID, "MX98357A") Name (_UID, Zero) Name (_DDN, "Maxim Integrated 98357A Amplifier") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 } Package () { "maxim,sdmode-delay", 100 } Package () { "sdmode-delay", 100 } } }) } } Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15017 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02i2c: Add a generic i2c driverDuncan Laurie
This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02drivers/intel/wifi: Add support for generating SSDT tableDuncan Laurie
Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but the wifi device is not described in devicetree.cb is tested to ensure it still generates the AML but does not include the _PRW wake pin. Example: devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end VPD: "region"="us" SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15019 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01drivers/lenovo: Add hybrid graphics driverPatrick Rudolph
Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01nau8825: Add driver for I2C codecDuncan Laurie
The Nuvoton NAU8825 audio codec is an I2C device that has a number of tunable parameters that can be provided to the kernel device driver for basic configuration and optimal operation. The configuration options are exposed to devicetree as registers and then presented as Device Properties via ACPI to the operation system. This sample configuration in devicetree: device pci 19.2 on chip drivers/i2c/nau8825 register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" register "jkdet_enable" = "1" register "sar_threshold_num" = "2" register "sar_threshold[0]" = "0x0c" register "sar_threshold[1]" = "0x1c" device i2c 1a on end end end Will generate the following code in the SSDT, trimmed for this commit message as there are more properties that can be configured: Scope (\_SB.PCI0.I2C4) { Name (_HID, "10508825") Name (_UID, Zero) Name (_DDN, "Nuvoton NAU8825 Codec") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit, "\_SB.PCI0.I2C4", 0, ResourceConsumer) Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"), Package () { Package () { "nuvoton,jkdet-enable", 1 }, Package () { "nuvoton,sar-threshold-num", 2 }, Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } } } }) } Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834 Reviewed-on: https://review.coreboot.org/15015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phaseHannah Williams
Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31drivers/net/r8168: Add driver for realtek nicDamien Zammit
One thing that is vital to this patch is the MAC address setting in case the EEPROM/efuse is unconfigured. Linux now recognises the default MAC address on GA-G41M-ES2L which does rely on the default bios settings for the MAC address. Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14927 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26drivers/intel/fsp2_0: Send post codes around calls to the blobsAlexandru Gagniuc
By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFSAndrey Petrov
Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-17drivers/intel/fsp1_1: Simplify union referencesLee Leahy
Simplify the union references to enable Coverity to properly process the routine. Found-by: Coverify CID 1349854 TEST=Build and run on Galileo Gen2 Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14870 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Replace for/break with returnsLee Leahy
Coverity does not like the use of for/break, switch to using returns instead. Found-by: Coverity CID 1349855 TEST=Build and run on Galileo Gen2 Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp2_0: Fix array indexing errorLee Leahy
Don't allow an array index of 2 to be processed by the code referencing the array. Found-by: Coverity CID 1353337 TEST=None Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14868 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-12drivers/intel/fsp2_0: Add timestamps around all calls to the blobAlexandru Gagniuc
Change-Id: I384cef0f5b4b71dbd7ad6d1d508e7c6395bf3f2d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-11cbfstool/fsp: Rename fsp1_1_relocateFurquan Shaikh
FSP 2.0 uses the same relocate logic as FSP 1.1. Thus, rename fsp1_1_relocate to more generic fsp_component_relocate that can be used by cbfstool to relocate either FSP 1.1 or FSP 2.0 components. Allow FSP1.1 driver to still call fsp1_1_relocate which acts as a wrapper for fsp_component_relocate. Change-Id: I14a6efde4d86a340663422aff5ee82175362d1b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-05-11util/cbfstool: Allow xip/non-xip relocation for FSP componentFurquan Shaikh
Currently, convert_fsp assumes that the component is always XIP. This is no longer true with FSP 2.0 and Apollolake platform. Thus, add the option -y|--xip for FSP which will allow the caller to mention whether the FSP component being added is XIP or not. Add this option to Makefiles of current FSP drivers (fsp1_0 and fsp1_1). Change-Id: I1e41d0902bb32afaf116bb457dd9265a5bcd8779 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09drivers/uart: Enable override for input clock dividerLee Leahy
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09spi: Add support for Winbond W25Q256Varadarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ifde289ec004f5d54d5df32011c87e49470e2bb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 613b5ae45f7b8325863d8be492a451e6d076e293 Original-Change-Id: I93386e058a60b5c9b61d89607cf8c6e0de6a21ca Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334522 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09lib/prog_loaders: Allow platforms to skip stage cacheFurquan Shaikh
Before multi-CBFS support was added, x86 platforms cached their ramstage in TSEG so that it could be re-used on the resume path. However, more resources/assets are being put in cbfs that are utilized during ramstage. Just caching ramstage does not mean that correct cbfs region is used for all the data. Thus, provide an option to allow platforms to skip caching any component for resume. Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-08parade/ps8640: Initialize edid_sizePatrick Georgi
decode_edid either gets EDID_LENGTH bytes or (in the extended case), 2*EDID_LENGTH. See that this is reflected in its size argument. Change-Id: If6c76358db4e9ee01c2bd2dbdd5948c61b7aa5bc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06rtc: Do checksum check for all bytesStefan Reinauer
Due to missing braces (that went undetected because of the indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 CMOS: add set_option() only takes the last changed byte into regard when determining whether the checksum needs to be updated. This bug went undetected for 5 years. Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06drivers/intel/fsp2_0: Update to FSP draft 9Andrey Petrov
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04drivers/xpowers: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Idae5ee5f1f48d904b704abe618165c0bec839979 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE usedAaron Durbin
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-04-28drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh
Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-22drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
The previous commit removed Kconfig, but not Makefile.inc Change-Id: If46a0a3e253eea9d286d8ab3b1a6ab67ef678ee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14419 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ricoh: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/generic: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ide0d48405d85ea2e889916f778e1556287651707 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/aspeed: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I8cf021ea5baff05eb5f84cc014612084afe3f858 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14053 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ati: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iba43630208be02603f4e0de5f62047bb3d23863a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14054 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/emulation: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I6e30a7be510c66fb1aa88314861d95f8ebe80377 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14056 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/i2c: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ia210e6832c18270043c0cb21b4881d9c802f3b2b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14058 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ics: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I40373768595a085bba9a5c934794e128f396828b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14059 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/aspeed: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I7a053ac1d8ecc3e443e91daeb406bae0b8c13323 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14060 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/sil: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ifc32b251677f8b75ffca224c0c900e9c34c756b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/xgi: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14049 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/parade: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I1313797d60925cc0627987936199e62073c264d7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ti: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08drivers/intel/fsp2_0: Add utility to recover MRC NV Storage dataHannah Williams
Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-08drivers/intel/fsp2_0: Add boot mode constantsAndrey Petrov
This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-07edid: Make framebuffer row alignment configurableJulius Werner
Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14267 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>