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2020-07-07drivers/intel/dptf: Add current participant Devices to DSDTTim Wawrzynczak
In this DPTF implementation, the participant device objects are written into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID, PTYP, and _STR). All other Methods & Names will be written into the SSDT. If a device is not used in any policy, then its _STA is set to return 0 ("off"). BUG=b:143539650 TEST=Compiles. Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07drivers/intel/mipi_camera: Add camera power resource to SSDTSugnan Prabhu S
This change adds support function to parse entries in the devicetree to generate PowerResource entries for the MIPI camera. Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add support to handle CIO2 deviceMatt Delco
This change updates mipi_camera driver to handle CIO2 device type. Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42470 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: SSDT changes to add PLDMatt Delco
This change updates mipi_camera driver to add PLD section to SSDT. Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42469 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: SSDT changes to add DSMMatt Delco
This change updates mipi_camera driver to add DSM section to SSDT. Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42468 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add support for camera sensor in SSDTMatt Delco
This change updates mipi_camera driver to handle camera sensor. Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42467 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Handle NVM and VCM device typeMatt Delco
This change adds support in mipi_camera driver to handle NVM and VCM device types. Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42466 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Handle acpi_name and common codeMatt Delco
This change updates the mipi_camera driver to handle acpi_name based on device_type, if acpi_name is not set in the devicetree and moves some of the common code to separate methods. Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06drivers/ipmi: Increase BMC waiting message level from DEBUG to INFOPaul Menzel
As the booting the system can be delayed for a noticeable amount of time, often 60 seconds is the default, this is not a debug message. Chose log level BIOS_INFO. Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-05drivers/pc80/tpm: Remove support code if TPM is disabledKyösti Mälkki
Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner
2020-07-05drivers/pc80/tpm/tis: Add x86_64 supportPatrick Rudolph
Fix integer with different size to pointer conversion on x86_64. Change-Id: Ic06a32d549b694310f4c724246f28fed15acf83f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42983 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU dataJohnny Lin
It implements the SMBIOS IPMI FRU mapping table defined in https://www.opencompute.org/documents/facebook-xeon-motherboard-v31 22.3 SMBIOS FRU mapping table. Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE. For type 11 string 1 to 6 are common and implemented in this driver, the rest are project dependent and can be added in the mainboard code. Tested on OCP Tioga Pass. Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40308 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04lib/coreboot_table: Add Intel FSP version to coreboot tableJohnny Lin
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION when PLATFORM_USES_FSP2_0 is selected. Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120" Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-04drivers/pc80/tpm: Remove LPC_TPMKyösti Mälkki
Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm is present in devicetree.cb it is necessary to always include the driver in the build. Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-04drivers/ipmi: Add IPMI KCS support in romstageJohnny Lin
It's necessary to run IPMI commands in romstage for writing error SEL such as memory initialization error SEL, and also for other usages such as starting FRB2 timer, OEM commands, etc. Add CONFIG_BMC_KCS_BASE for BMC KCS port address that can be used across romstage and ramstage. Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40234 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03drivers/intel/pmx_mux: Remove redundant declarationKyösti Mälkki
Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41871 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02acpi_device: Replace polarity with active_low in acpi_gpio for GpioIoFurquan Shaikh
As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02drivers/generic/gpio_regulator: Drop unused driver for gpio_regulatorFurquan Shaikh
Proposal for gpio_regulator usage in ACPI never got accepted upstream for Linux kernel. So, the gpio_regulator driver in coreboot remains unused. This change drops this unused driver. Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30src/drivers/intel: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429979, 1429982 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42835 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28drivers/ipmi: Read more FRU data fields for Product and Board InfoJohnny Lin
Tested on OCP Tioga Pass Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40522 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28gpio_keys: Allow boards to configure different wakeup routesFurquan Shaikh
This change allows mainboard to configure different wakeup routes that can be used by a GPIO key: 1. SCI: This is selected when SCI route is used to wake the system. It results in _PRW property being exposed in ACPI tables. 2. GPIO IRQ: This is selected when GPIO controller wake is used to wake the system. It is typically used when the input signal is not dual routed and the GPIO controller block is not capable of applying filters for IRQ and wake separately. In this case, _PRW is not exposed in ACPI tables for the key device. 3. Disabled: No wakeup supported. Based on these wakeup routes, gpio_keys_add_child_node() is updated to expose _PRW and _DSD properties for wakeup appropriately. Additionally, the change updates mainboards that were already using gpio_keys to set wakeup_route attribute correctly and renames "wake" to "wake_gpe" to make the usage clear. BUG=b:159942427 Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-25drivers/ipmi: Add IPMI read FRU chassis info areaJohnny Lin
Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Chassis Info Area. Tested on OCP Tioga Pass. Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40306 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25drivers/ipmi: Add function read_data_string() to make code cleanerJohnny Lin
Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1da8abaa682af802e5cda65e5021069daf4ee717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22spi/winbond: Simplify status reg union typesDaniel Gröber
Having speparate types for the status register with three and four block protection bits respectively doesn't really make sense, it's the same size either way just a different representation, so one union type will do. This allows us to de-duplicate the status register read in winbond_get_write_protection as well as removing another layer of union in 'struct status_regs'. Change-Id: Ie99b98fb6762c8d84d685b110cfc2fd5458b702e Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42111 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22lockdown: Add Kconfigs for SPI media protection modeDaniel Gröber
SPI_WRITE_PROTECTION_REBOOT seems to be a Winbond thing, other vendors such as Macronix only support permanent protection but conditional on the WP# pin state. Change-Id: Iba7c1229c82c86e1303d74c7bc8f89662b5bb58c Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41747 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22drivers/intel/gma/intel_ddi.c: Clean upElyes HAOUAS
Remove unused includes. Change-Id: I91dd92b54822dd0d10051ccd600ce787860c8ff6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-21src: Substitute `__FUNCTION__` with `__func__`Angel Pons
The former is not standard C, and we primarily use the latter form. Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-06-20ACPI: Drop some HAVE_ACPI_RESUME preprocessor useKyösti Mälkki
Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-18ACPI,drivers/: Do not guard <acpi/acpi.h>Kyösti Mälkki
Header was moved outside arch/. Change-Id: Id96c2bdcee49cddab6610c7e2cd6f07638279256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-17treewide: Replace CONFIG(ARCH_xx) testsKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17smmstore: Verify userspace-provided pointer to protect SMMPatrick Rudolph
Use the introduced functions and verify pointers in the SMMSTORE. Make sure to not overwrite or leak data from SMM and update the documentation as well. Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15Makefile.inc: Remove all-y with CONFIG_ARCH_xx guardsMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. As a generalization, remove all-y for CONFIG_ARCH_xx guarded makefiles. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14drivers/intel/fsp2_0: Add FSP 2.2 specific supportSubrata Banik
• Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14dptf: Introduce new paradigm for configuring DPTF parametersTim Wawrzynczak
Currently, configuring and reviewing DPTF parameters is difficult because DPTF tables and methods are defined in static ASL files, and are littered with #ifdefs which both define parameters and influence behavior (e.g., whether a method is included or not). This patch train is an effort to bring DPTF support to our ACPI DSDT/SSDT generation framework. This first patch is very minimal, and includes only creation of the DPTF device (in the DSDT). BUG=b:143539650 TEST=compiles (later tests get more comprehensive). Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10drivers/intel/fsp2_0: Allow SoC/mainboard to update NvsBufferPtrFurquan Shaikh
This change moves the check for NvsBufferPtr in S3 resume case to happen just before FSP-M is called. This allows SoC/mainboard code to set NvsBufferPtr if it doesn't use the default MRC cache driver. BUG=b:155990176 Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-10binaryPI: Replace CONFIG(ARCH_xx) testKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Not strictly required for binaryPI boards, but do this for consistency. Change-Id: Id0bbbfb6f695c4bb920bc57a1e9362a23884efb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-08spi: Remove non_volatile flag from block protection interfaceDaniel Gröber
Only Winbond parts seem to support making status register writes volatile. So this flag should not be exposed in the generic interface. Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07drivers/mrc_cache: generate debug messages for MRC cache updateJonathan Zhang
When MRC cached data update is performed, messages are written to event log, which is flash based. For system that does not have flash based event log, the messages are lost. Added corresponding BIOS_DEBUG messages. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1ef4794151fea7213c8317ddc898b0e37da280b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41981 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
Change-Id: I3f08b9cc34582165785063580b3356135030f63e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-04drivers/uart/acpi: Add new device driver for UART attached devicesDuncan Laurie
This driver generates an ACPI device object for a UART attached device with all of the expected device support handlers like different interrupt sources and power control GPIOs. Example use: chip drivers/uart/acpi register "name" = ""UDEV"" register "desc" = ""UART Attached Device"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cros-ec-uart"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)" register "uart" = "ACPI_UART_RAW_DEVICE(115200, 64)" device generic 0 on end end Resulting in this ACPI device: Device (UDEV) { Name (_HID, "PRP0001") Name (_UID, Zero) Name (_DDN, "UART Attached Device") Method (_STA, 0, NotSerialized) { Return (0x0F) } Name (_CRS, ResourceTemplate () { UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.PCI0.UAR2", 0x00, ResourceConsumer, , Exclusive) GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer) { 0x0114 } }) Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) { Package (0x02) { "compatible", "google,cros-ec-uart" } } }) } Change-Id: Idfd2d9d2ab6990a82ddd401734c0d9b1b0b8f82d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-03drivers/generic/max98357a: Don't write device if HID is missingRaul E Rangel
If the device is missing the HID, the code would previously leave an open scope and device on the stack. BUG=b:154756391 TEST=Verify stack ACPI stack does not exceed limit on Trembyle. Fixes: a1c82c5ebee ("drivers/generic/max98357a: Allow custom _HID from config") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02arch/x86/postcar_loader: utilize var_mtrr_context APIAaron Durbin
Now that there is a generic solution in mtrr subsystem utilize the API. BUG=b:155426691,b:155322763 Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cbfs.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cbfs.h>' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include <cbfs.h>' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 17:57:58 +0000