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2017-11-28spi/tpm.c do not waste time on wake pulses unless necessaryVadim Bendebury
The Cr50 secure chip implementation is guaranteed not to fall asleep for 1 second after any SPI slave activity. Let's not waste time on the wake up ping when it is not necessary. BRANCH=cr50 BUG=b:68012381 TEST=using a protocol analyzer verified that the wake pulses are generated only when the new coreboot stage or depthcharge start, not on every SPI slave transaction. Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-27drivers/net: add SSDT ACPI declaration and WOL featureGaggery Tsai
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and also _PRW for WOL feature. Besides, adds a wake variable in chip information. BUG=b:69290148 BRANCH=None TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168 chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW are filled correctly && put system into S3 && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL package. Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22drivers/i2c/tpm/cr50: Simplify and increase init delay to 30 secondsDuncan Laurie
The Cr50 i2c driver provides separate entry points for probing and initialization, but probing function does not really do much. It also claims and releases locality on every coreboot stage, but there is no need for this - locality should be definitely claimed after reset and then it could be retained through the boot process. On top of that the driver does not properly account for long time it could take the Cr50 chip to come around to reset processing if TPM reset request was posted during a lengthy TPM operation. This patch addresses the issues as follows: - tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept around to conform to the expected driver API. - tpm_vendor_init() invokes a function to process TPM reset only in the first stage using TPM (typically verstage), the function checks if locality is claimed and if so - waits for it to be released, which indicates that TPM reset processing is over. - before claiming locality check if it is already taken, and if so - just proceed. BRANCH=none BUG=b:65867313, b:68729265 TEST=Verified that reef no longer hangs during EC reboot and firmware_Cr50ClearTPMOwner (not yet merged) tests. Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21spi/tpm: claim locality just once during bootVadim Bendebury
All coreboot stages using TPM start with the same sequence: check if locality is claimed, if so, release it by writing 'active locality' bit, then try claiming it. This is actually not a proper procedure: section "5.5.2.3.1 Command Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification Level 00 Revision 00.430 Family 2" lists overwriting active locality status bit as a means of triggering TPM command abort. On top of that, none of the coreboot stages releases locality, it is enough to claim it once when device starts booting. In fact, locality being active when the device is in verstage is most likely due to delayed TPM reset processing by the Cr50 TPM: reset is an asynchronous event, and is processed once current command processing completes. The proper procedure is to wait if locality is active until it is released (which will happen when Cr50 processes reset) and then proceed to claim it. This needs to happen only during verstage, other stages using TPM are guaranteed has been claimed earlier. BRANCH=gru BUG=b:65867313 TEST=the new autotest triggering EC reset during key generation process does not cause boot failures on Fizz device any more. Below are times verstage had to wait: TPM ready after 3132 ms TPM ready after 22120 ms TPM ready after 4936 ms TPM ready after 6445 ms TPM ready after 11798 ms TPM ready after 27421 ms TPM ready after 4582 ms TPM ready after 7532 ms TPM ready after 27920 ms TPM ready after 3539 ms TPM ready after 12557 ms TPM ready after 6773 ms TPM ready after 1631 ms TPM ready after 197 ms TPM ready after 24330 ms TPM ready after 3241 ms Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-16drivers/spi/tpm: Poll TPM_VALID bit until validShelley Chen
In case the TPM is doing a long crypto operation the initial probe could be very delayed. Rather than end up in recovery make the delay long enough to accommodate the (current) long crypto times. This would add a maximum of 30 seconds to boot time. Mirroring changes done on i2c side in CL:756918 BUG=b:65867313, b:68729265 BRANCH=None TEST=Make sure fizz boots up Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09drivers/i2c/tpm/cr50: Increase init delay to 30 secondsDuncan Laurie
In case the TPM is doing a long crypto operation the initial probe could be very delayed. Rather than end up in recovery make the delay long enough to accommodate the (current) long crypto times. BUG=b:65867313, b:68729265 TEST=Verified that Soraka no longer hangs during EC reboot test. Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-03siemens/nc_fpga: Set FW_DONE bit before jumping to payloadWerner Zeh
Once coreboot is ready and payload has been loaded a bit inside the NC FPGA needs to be set to notify this event. As there are NC FPGAs with different PCI device IDs save the BAR0 address in a global variable once the driver evaluates this address. It can then be used to access the register from the boot state machine callback without the need of searching for all possible PCI devices again. As this driver is only used at ramstage there is no need of using CAR_GLOBAL for the global variable. Use a Kconfig switch to make this feature selectable from mainboard as not every mainboard may have a FPGA with that capability. Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03drivers/intel/fsp2_0/hob_verify: Correct conversion specifierPaul Menzel
Use the correct conversion specifier for `size_t` to fix the error below. ``` src/drivers/intel/fsp2_0/hob_verify.c:31:4: error: format '%lx' expects \ argument of type 'long unsigned int', but argument 4 has type \ 'size_t {aka unsigned int}' [-Werror=format=] "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", ^ range_entry_size(&tolum), cbmem_overhead_size()); ~~~~~~~~~~~~~~~~~~~~~ ``` Found-by: gcc (Debian 7.2.0-8) 7.2.0 Change-Id: I4631672211095f9934925e9bd230ccbf63c736af Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-01spi/tpm: Make sure AP properly syncs up with Cr50Vadim Bendebury
When Cr50 TPM is being reset, it continues replying to the SPI bus requests, sends wrong register values in response to read requests. This patch makes sure that the TPM driver does not proceed unless proper value is read from the TPM device identification register. If the read value is still wrong after 10 retries taken with 10 ms intervals, the driver gives up and declares TPM broken/unavailable. BRANCH=cr50 BUG=b:68012381 TEST=ran a script resetting the Fizz device as soon as the "index 0x1007 return code 0" string shows up in the AP console output. The script keeps rebooting the Fizz indefinitely, before this script Fizz would fail to read TPM properly and fall into recovery after no more than four reboots. Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01drivers/net/r8168: Add customized LED modeGaggery Tsai
This patch adds a function to program a customized LED setting for Realtek 81xx family. It reads the settings from devicetree under target board and programs the setting to offset 0x18 and 0x19. BUG=b:65437780 TEST=Add customized_leds register in devicetree.cb under target board, enable RT8168_SET_LED_MODE flag. Make sure the setting is programmed correctly to offset 0x18 and 0x19. Observed the LEDs were behaving as expected. Executed suspend/resume and the LEDs were still working as expected. Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber
The current header `i915.h` is too invasive to be used everywhere where we want to use *libgfxinit*. Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-23drv/intel/gma/opregion: fix opregion version for WindowsMatt DeVillier
Although Intel's current spec[1] shows the OpRegion structure version as being the top 16 bits of the field, Intel's Windows drivers require the OpRegion structure version to be in the top 8 bits of the field when not using a VGA BIOS (eg, NGI or GOP driver). As the Linux i915 driver only checks that the version is >= 2, there is no change in functionality there. This change effectively matches Intel's implementation in TianoCore, where the version is set to 0x0200 << 16. [1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and Legacy mode with libgfxinit, observe Intel GPU driver functional. Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22intel/i210: Set bus master bit in command registerWerner Zeh
There are still Ethernet drivers out there in the wild which expect that the master enable bit was set by firmware. A missing master enable bit will lead to a non-functional driver. Though it is clear the task of the driver to set this bit it is too late now. So work around this issue on firmware level...again! Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-19elog: Support logging S0ix sleep/wake info in elogFurquan Shaikh
1. Add support for new GSMI commands to log S0ix entry/exit information in elog. 2. In case of resume, provide callbacks to allow platform and mainboard to log any wake source information. BUG=b:67874513 Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16drivers/elog: Fix debug build errorsJohn E. Kabat Jr
Add hexdump.c to Makefile.inc and change an elog_debug format to use %z for size_t arguments. This corrects build errors when ELOG_DEBUG is used. Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16console/flashconsole: Enable support for postcarYouness Alaoui
If FSP 2.0 is used, then postcar stage is used and the flashconsole as well as spi drivers needed to be added. Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16drivers/uart8250mem: Check for zero base addressMarshall Dawson
Before adding a new UART to the coreboot/lb table, verify that it has a non-zero base address. This is consistent with all other functions that use the uart_platform_base() function. This was tested on google/kahlee by using an invalid UART number and forcing the base address to 0. Execution was able to complete through depthcharge and into the OS. Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21996 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13drv/intel/gma/opregion: Add common init_idg_opregion()Matt DeVillier
Add a new common method to initialize ACPI OpRegion. * Try to locate vbt.bin in CBFS. * Try to locate VBIOS in CBFS. * Keep existing code to probe at 0xc0000. Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at 0xc0000. Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS). In all cases linux was successfully provided with VBT from ACPI opregion. Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-06soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbtPatrick Georgi
All callers of locate_vbt just care about the file content and immediately map the rdev for its content. Instead of repeating this in all call sites, move that code to locate_vbt. Change-Id: I5b518e6c959437bd8f393269db7955358a786719 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05drivers/intel/fsp2_0: use common code to fetch vbt.binPatrick Georgi
No need for having two of everything in the coreboot codebase. Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-28siemens/nc_fpga: Move some parameters to another functionMario Scheithauer
For general use of this driver it is necessary to move some parameters from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any functional change. Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28drivers/usb/Kconfig: remove USBDEBUG_DONGLE_BEAGLEBONE_BLACKFelix Held
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it also should be selected for the BeagleBone Black. Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/21486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-14usbdebug: Fix init and add support for postcarKyösti Mälkki
It was originally designed such that if usbdebug_init() was called before cbmem_initialize(), it would fetch the already-initialized state from CBMEM. This changed when cbmem_find() behaviour changed to require cbmem_initialize() to be called first. As a result, ramstage had to reinitialize all of the EHCI controller and USB endpoints on entry. This was slow, specially with AMD hardware where one can scan USB ports to probe for the debug dongle. For postcar and ramstage, move usbdebug entry such that it is triggered from CBMEM_INIT_HOOK instead of console_init(). Side-effect of this is usbdebug console shows 'coreboot-xxx ... starting...' line only for romstage. Initialisation for usbdebug is never done in postcar. If you have USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on usb either. While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE and alike. Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13fsp1_0/fsp_util: Rename global symbol find_fspDamien Zammit
To avoid error with symbol redefinition (using clang): src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition ".global find_fsp\n\t" Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp. Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08drivers/intel/fsp1_1: Adjust check for FSP header revisionMatt DeVillier
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1 header files, so adjust the header revision check to ensure that the FSP blob isn't newer than the header, rather than an exact version match. This resolves a version mismatch issue with Braswell ChromeOS devices, which ship with FSP blobs newer than the publicly-released blob (1.1.2.0), but older than the current Braswell FSP 1.1 header (1.1.7.0). TEST: build/boot google/cyan and edgar boards, observe no adverse effects from using current FSP header (1.1.7.0) with the factory- shipped FSP blobs (1.1.4.0/1.1.4.2). Change-Id: I8934675a2deed260886a83fa34512904c40af8e1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06driver/i2c/max98927: Add imon and vmon paramsHarsha Priya
This change list adds imon and vmon slot numbers as params for Maxim 98927 driver. These values are looked up in the kernel driver to confiure IV feedback for audio playback on speakers. BUG=b:36724448 TEST=After boot, the register dump for Max98927 codecs should have imon and vmon slots numbers set in 0x1e register. Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-04Kconfig: Move and rename ADD_VBT_DATA_FILEPatrick Rudolph
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to INTEL_GMA_ADD_VBT_DATA_FILE. Depend on Intel platforms to avoid confusing users of non-Intel platforms. The Intel GMA driver will use the vbt.bin, if present, to fill the ACPI OpRegion. Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-30acpigen: Add stop gpio control to power resourceFurquan Shaikh
There is at least one I2C device (being used by Soraka) that has 3 controls -- enable, reset and stop. If the stop gpio is not put into the right state when turning off the device in suspend mode, then it causes leakage. Thus, we need control in power resource to be able to stop the device when entering suspend state. BUG=b:64987428 TEST=Verified on soraka that touchscreen stop is correctly configured on suspend. Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21249 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30drivers/i2c/ck505: Add generic driver to configure clockgenArthur Heymans
Replaces the ics/954309 driver with a more generic version to accommodate clockgens with a different amount of registers. It also features a mask to only touch certain bits of the clockgen. TODO: set appropriate mask for X60/T60 since the datasheets for their clockgens can be found. Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-30drivers/i2c/generic: Support additional device propertiesDuncan Laurie
Add support for providing additional free form device properties via devicetree in order to make this driver suitable for kernel drivers that need additional board-specific device properties. This currently allows adding up to 10 additional properties to a device. BUG=b:63413023 TEST=manual testing to ensure that newly added properties are in SSDT Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLESubrata Banik
This patch to ensure that coreboot is able to store memory training data into SPI and perform platform lockdown after PCI enumeration is done before handing over control to NotifyPhase() - Post PCI enumeration. Modified coreboot bootstate execution order below: BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration TEST=Please find test case and results for Chrome Devices as Apollolake- Reef, Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS. 1. Without patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Chrome CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. 2. With patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Yocto CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there is no noticeable difference. On a reboot, suspend resume from Chrome console, the mrc cache is found, and utilized. Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18drivers/i2c/rx6110sa: Drop I2C interface arbitrationNico Huber
Change-Id: Ib31e77eec639c231520198c0b978d6c3c1eadaed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17arch/x86: Make postcar TempRamExit call genericMarshall Dawson
Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-11driver/intel/gma: Allow use of GFX_GMA_ANALOG_I2C_HDMI_x in C NGIArthur Heymans
These Kconfig options can be reused for the same purpose of selecting the correct i2c pins for probing the analog output EDID in C native graphic init. For this purpose this patch makes those options independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT. Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
Migrate opregion code from northbridge/intel/common to drivers/intel/gma in preparation for consolidation with soc/intel/common opregion code. Rename init_igd_opregion() for clarity and disambiguation with other implementations. Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-10fsp2_0/mma: Enable EvLoader in FSP for MMAPratik Prajapati
EvLoader is FSP module which loads and runs MMA tests. With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader needs to be enabled with UPD param from coreboot. Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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