summaryrefslogtreecommitdiff
path: root/src/drivers
AgeCommit message (Collapse)Author
2015-09-10fsp1_1: provide binding to UEFI versionAaron Durbin
FSP has some unique attributes which makes integration cumbersome: 1. FSP header files do not include the types they need. Like EDKII development it's expected types are provided by the build system. Therefore, one needs to include the proper files to avoid compilation issues. 2. An implementation of FSP for a chipset may use different versions of the UEFI PI spec implementation. EDKII is a proxy for all of UEFI specifications. In order to provide flexibility one needs to binding a set of types and structures from an UEFI PI implementation. 3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h file which defines it's own types. Commonality between FSP chipset implementations are only named typedef structs. The fields within are not consistent. And because of FSP's insistence on typedefs it makes it near impossible to forward declare structs. The above 3 means one needs to include the correct UEFI type bindings when working with FSP. The current implementation had the SoC picking include paths in the edk2 directory and using a bare <uefi_types.h> include. Also, with the prior fsp_util.h implementation the SoC's FSP FspUpdVpd.h header file was required since for providing all the types at once (Generic FSP 1.1 and SoC types). The binding has been changed in the following manner: 1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1 selects. No other bindings are currently available, but this provides the policy. 2. Based on CONFIG_UEFI_2_4_BINDING the proper include paths are added to the CPPFLAGS_common. 3. SoC Makefile.inc does not bind UEFI types nor does it adjust CPPFLAGS_common in any way. 4. Provide a include/fsp directory under fsp1_1 and expose src/drivers/intel/fsp1_1/include in the include path. This split can allow a version 2, for example, FSP to provide its own include files. Yes, that means there needs to be consistency in APIs, however that's not this patch. 5. Provide a way for code to differentiate the FSP spec types (fsp/api.h) from the chipset FSP types (fsp/soc_binding.h). This allows for code re-use that doesn't need the chipset types to be defined such as the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Signed-off-by: Aaron Durbin <adubin@chromium.org> Change-Id: I894165942cfe36936e186af5221efa810be8bb29 Reviewed-on: http://review.coreboot.org/11606 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-09-10FSP: Pass FSP image base address to find_fspLee Leahy
Add a parameter to find_fsp which is the image base address. Adjust the fake stack in cache_as_ram.inc to pass in the read-only FSP image base address. In fsp_notify, pass in the read-only FSP image base address when the FSP header pointer is NULL. In find_fsp, validate the FSP binary image starting from the specified image base address. BRANCH=none BUG=None TEST=Build and run on Skylake Change-Id: Iac43c8aac8491390479af551765b514ca919928a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95 Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295593 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09drivers/pc80: Do not initialize PS2 keyboard by defaultAlexandru Gagniuc
The most common payloads do not need this set, so optimize for the common case. Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-09-08drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO levelDuncan Laurie
Having no supplied printk level makes this info message printed at all levels and so it shows up when booting with DEFAULT_CONSOLE_LOGLEVEL=3. BUG=chrome-os-partner:40635 BRANCH=none TEST="USE=quiet-cb emerge-glados coreboot" Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77 Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297336 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11559 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08drivers/intel/fsp1_1: Take platform ID as a string, not integersAlexandru Gagniuc
The platform ID is an 8 character ASCII string, so our config should take it in as a string, rather than a set of two 32-bit integers. Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-09-07intel: Do not hardcode the position of mrc.cacheAlexandru Gagniuc
The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-05qemu: fix vga driver buildGerd Hoffmann
Commit "7dbf9c6 edid: Use edid_mode struct to reduce redundancy" moved some fields from "struct edid" to "struct edid_mode". Adapt the bochs and cirrus drivers to that change. Change-Id: I9ec82a403d0264955d4b72496219036c7775c758 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/11502 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-04bootstate: remove need for #ifdef ENV_RAMSTAGEAaron Durbin
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however the current state of the header meant bad build errors in non-ramstage. Therefore, people had to #ifdef in the source. Remove that requirement. Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11492 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-04x86: remove cpu_incs as romstage Make variableAaron Durbin
When building up which files to include in romstage there were both 'cpu_incs' and 'cpu_incs-y' which were used to generate crt0.S. Remove the former to settle on cpu_incs-y as the way to be included. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. No include file changes. Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-31drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macroAlexandru Gagniuc
Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11464 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-31drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairsAlexandru Gagniuc
The #error messages only say that "CONFIG_* must be defined", which conveys no more information that the compiler or assembler failing when it encounters an undefined CONFIG_* symbol. Change-Id: I6058474d4cd454cfc20290650425d379f388abd9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11461 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-29intel/fsp1_1/hob.c: Refactor file to match coreboot coding styleAlexandru Gagniuc
Avoid ASSERT() when a better solution exists, avoid UPPERCASE types when C99 types exist, and use stdlib functions where possible. Change-Id: Ia40ec8ff34ec82994b687d517dc4b145fb58716c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29drivers/intel/fsp1_1: Don't compile GOP support in romstageAlexandru Gagniuc
We don't need the code in romstage, and it saves us a few #ifdefs. Change-Id: I26d867566f07c7d80890cd01bf055be7497130d3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29fsp1_1: remove duplicate mrc caching mechanismAaron Durbin
For some reason fsp 1.1 has a duplicate mechanism for saving mrc data as soc/intel/common. Defer to the common code as all the existing users were already using the common code. BUG=chrome-os-partner:44620 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I951d47deb85445a5f010d23dfd11abb0b6f65e5e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Original-Commit-Id: 2138b6ff1517c440d24f72a5f399bd6cb6097274 Original-Change-Id: I06609c1435b06b1365b1762f83cfcba532eb8c7a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295236 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11454 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-14fsp1_1: fsp_relocate: use struct region_device and struct progAaron Durbin
Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Reviewed-on: http://review.coreboot.org/11193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13uart8250mem: provide uart_fill_lb()Aaron Durbin
There was no implementation for uart_fill_lb() in the 8250mem driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are employed then the build doesn't fail. BUG=chrome-os-partner:43419 BRANCH=None TEST=Built with glados using 8250MEM Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289899 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I972b069a4def666f509268816de91ed6c0f655d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11169 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09drivers/pc80/i8254.c: Indent with GNU indent 2.2.11Paul Menzel
Run `indent -linux src/drivers/pc80/i8254.c` and manually put the `;` in the while loop back on a separate line. Change-Id: I58c4c5df3846a91ef92aafb608962dc26a21f811 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10452 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-29arm, arm64, mips: Add rough static stack size checks with -Wstack-usageJulius Werner
We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21console: Add UART8250MEM 32bit supportNaveen Krishna Chatradhi
This patch adds UART8250MEM_32 feature flag to support UART8250 compatible with 32bit access in memory mapped mode. [pg: rebuilt to reuse the existing UART8250 8bit access driver which reduces code duplication.] Change-Id: I310e70dfab81dcca575e9931e0ccf93af70efa40 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c3b2c628b854e8334540ff5158c2587dbfabf95 Original-Change-Id: I07ee256f25e48480372af9a9255bf487c331e51d Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-12Verify Kconfigs symbols are not zero for hex and int type symbolsMartin Roth
For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead check to make sure they're defined and not zero. In some cases, zero might be a valid value, but it didn't look like zero was valid in these cases. Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-10FSP 1.1: Update the CBFS image typeLee Leahy
Update Makefile.inc to use the simplified CBFS image type. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ibb8413ab90b147e9d26d32639a8822c57ca54a46 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-30drivers/i2c/tpm: move tpm driver around a bit more.Patrick Georgi
The many different places to put vboot support in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: Idddb9f5e2ef7bcc273f429d9f432bd37b4573567 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10728 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30drivers/i2c/tpm: push tpm driver from verstage to libverstagePatrick Georgi
That way it's available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I0665e297f199acd60cff93e1b39812f183115d33 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-27Kconfig: Remove unnecessary and incorrect MRC_CACHE symbolsMartin Roth
Because of a misunderstanding of how Kconfig files are parsed, the OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value was correctly set. This is not needed unless for some reason the Kconfig parser is suddenly rewritten to parse everything differently. At some point, the value in the FSP's Kconfig file was updated to OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard Kconfig files were not updated. This resulted in the default values not getting set correctly by default on the FSP Bay Trail boards. This removes the whole bunch of incorrect and unnecessary symbols and just sets the default for the MRC cache location directly. Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10611 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-25Intel FSP 1.1: Move Kconfig comment inside 'if' blockMartin Roth
- Move the 'Intel FSP' Kconfig comment inside the 'if' block so that it doesn't show up on platforms that aren't using it. - Update the comment to reflect that this is version 1.1 of the FSP interface. Change-Id: I7182c5b07332c4f95620f7374526ab1de0484d01 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10650 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-24FSP 1.1: Bring source up-to-dateLee Leahy
Use 3rdparty/blobs subdirectory for binary files Display the MTRRs after TempRamExit and before the MTRR setup Clear all of the variable MTRRs before the MTRR setup Define the FSP attributes location and bits Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the FSP_BOOTLOADER_TOLUM_HOB. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-11lenovo: Hide SMBIOS configVladimir Serbinenko
It's derived from EEPROM on Lenovo machines and not from user config which is ignored. Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7055 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-06-09cbmem: add indicator to hooks if cbmem is being recoveredAaron Durbin
It can be helpful to certain users of the cbmem init hooks to know if recovery was done or not. Therefore, add this as a parameter to the hooks. Change-Id: I049fc191059cfdb8095986d3dc4eee9e25cf5452 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() APIKyösti Mälkki
Squashed and adjusted two changes from chromium.git. Covers CBMEM init for ROMTAGE and RAMSTAGE. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7878 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-07Fix Kconfig whitespace.Martin Roth
All other Kconfig locations start with tabs. Change-Id: I0ee5f0b0b82f85c8ae58b3626f142f159554efb3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10438 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Idcd059f05523916f726b94931c2487ab028b7d72 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10409 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-02tpm: Add dummy _DSM to make Bitlocker happy.Vladimir Serbinenko
Change-Id: Ieb6f70f5b2863336bd6143b2dfbb1d67c4c26109 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02Hide PLATFORM_USES_FSP1_1.Vladimir Serbinenko
This should be an internal selectable variable rather than user-visible config. Moreover the description is misleading. This is a typical case of an option "Should it work?" where there is only one right answer yet we still ask it. Change-Id: Idc0ce2e1b9f89eddd034966cc877483d994ce0eb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02TPM: Add Infineon SLB9670 SPI TPM supportWenkai Du
This patch provides support for TPM Infineon SLB9670 by adding its device ID to the list. BRANCH=None BUG=chrome-os-partner:40640 TEST=Built and test SLB9670 on SKL U Reference board Fab 2 Change-Id: I2d26fc6c7d074881f2e6189e1325808544b7d26d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c92884be75b631c302801e162292c245ed7bf5d Original-Change-Id: I4607fc96f70175b2461b40ba61e7a821e187de40 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274053 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-29tpm: Add Infineon TPM 1.2 supportSubrata
This patch provides support for TPM Infineon TT1.2 devices by enumerating the TT1.2 ID in the Infineon device list. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271256 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10302 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-29tpm: Fix multiple device supportSubrata
Current TPM driver does not support multiple devices for a given vendor. As the device object never takes the 2nd ID in the list. This patch fixes the same. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2 Original-Signed-off-by: Subrata <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271727 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar@intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com> Reviewed-on: http://review.coreboot.org/10303 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-28Remove leftover tseg_relocateVladimir Serbinenko
Change-Id: I534f992ed479c7cdc049bd598259b1f1cf2953b9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10354 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-28Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10322 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-27Deactivate TPMVladimir Serbinenko
Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23Hide TPM_TIS_BASE_ADDRESSVladimir Serbinenko
TPM_TIS_BASE_ADDRESS is technical setting, shouldn't be user-visible. Change-Id: Ibf74f52be16fb7d2cfa78419087a4c3e7607368a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10271 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-23drivers/intel: Update FSP 1.1 DriverLee Leahy
Update the FSP driver files from 1.0 to 1.1. Updates will occur manually to these files only for FSP 1.1 support. An fsp_x_y should be added in the future to support newer versions of the FSP specification. Please note that due to the interface with EDK2, these files make references to data structures and fields that use CamelCase. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: I2914c047d786a3060075356783ac9758bc41f633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 18:38:38 +0000