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2015-04-10TPM: Reduce buffer size to fix stack overflowJulius Werner
The TPM driver by default allocates a 4K transfer buffer on the stack, which leads to lots of fun on boards with 2K or 3K stack sizes. On RK3288 this ends up writing over random memory sections which dependent on the memlayout of the day might contain timestamp data (no big deal) or page tables (-> bad time). This patch fixes the problem by reducing the buffer size to slightly above 1K, which still seems to work as far as I can tell. There was already some really odd code that #undef'ed this value and redefined it with the lower number in one .c file (unfortunately not the one with the buffer declaration), with no explanation whatsoever... I'm removing that and just assume the smaller value will be fine for everything. BRANCH=veyron BUG=None TEST=Booted Pinky and Falco. Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81 Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236976 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
This is being triggered because the base address is added, but there is nothing that needs done with it in set_resources step and the ERROR message is tripping suspend resume test scripts. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=boot on samus and check for ERROR strings, successfully run suspend_stress_test without failures Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231603 (cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3 Original-Reviewed-on: https://chromium-review.googlesource.com/231604 Original-Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
This adds a ramstage driver for the TPM and allows the interrupt to be configured in devicetree.cb. The interrupt vector is set like other PNP devices, and the interrupt polarity is set with a register configuration variable. These values are written into locality 0 TPM_INT_VECTOR and TPM_INT_ENABLE and then all interrupts are disabled so they are not used in firmware but can be enabled by the OS. It also adds an ACPI device for the TPM which will configure the reported interrupt based on what has been written into the TPM during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM is enabled, and the _CRS method will only report an interrupt if one has been set in the TPM itself. The TPM memory address is added by the driver and declared in the ACPI code. In order to access it in ACPI a Kconfig entry is added for the default TPM TIS 1.2 base address. Note that IO address 0x2e is required to be declared in ACPI for the kernel driver to probe correctly. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=manual testing on samus: 1) Add TPM device in devicetree.cb with configured interrupt and ensure that it is functional in the OS. 2) Test with active high and active low, edge triggered and level triggered setups. 3) Ensure that with no device added to devicetree.cb that the TPM is still functional in polling mode. Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Move the LPC TPM driver to a subdirectoryDuncan Laurie
This moves the LPC TPM driver to drivers/pc80/tpm so it can be turned into a ramstage driver with a chip.h It includes no other changes yet. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=emerge-samus coreboot Change-Id: Iac83e52db96201f37a0086eae9df244f8b8d48d9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: be2db391f9da80b8b75137af0fe81dc4724bc9d1 Original-Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10rtc: Add an RTC driver for the TI TPS65913 PMIC.Furquan Shaikh
The TPS65913 PMIC has an RTC built into it. This change adds a driver for it which implements the new RTC API. BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log verified across multiple boots. Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39 Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9425 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Hide elog_flash_offset_to_address() from SMMFurquan Shaikh
Change-Id: Iaef9d4755f07ca03ca823831c3272183b5d6aed1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9450 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Fix typecast issues related to 64-bit compilation.Furquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles successfully for ryu and nyan. Change-Id: I036fd42d5cd4b71bcb68eea0fdd9a4e1aa4711e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9424 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-10tpm: allow 0 as valid i2c bus numberDaisuke Nojiri
tpm driver uses bus=0 as indication of uninitialized tpm device. this change allows 0 as a valid i2c bus number. BUG=None BRANCH=ToT TEST=Built cosmos. Change-Id: Ie8d285abff11643cc3efc0fa30e4afcc3ca1c0d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 493077b68cf46b08f0d1ddfe57bf6064d714d537 Original-Change-Id: Iac55e88db4ef757a292270e7201d8fdd37a90b50 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9405 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29drivers/pc80/mc146818rtc_early: Honor Kconfig reboot count clear settingTimothy Pearson
Change-Id: I6426ea2ca1732a6edfae059fe5dbf4f398bc9b98 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9155 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28drivers: add GIC supportAaron Durbin
The GIC is ARM's "Generic Interrupt Controller". This change essentially implements the rudimentary support for a GICv2 implementation that routes all interrupts to Group1. This should also work for GICv1 with security extensions. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel using the code. Change-Id: I9c9202c1309ca9e711e00d742085a6728552c54b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d1cd9b6b76035af107b7dc876f90777698162d34 Original-Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217512 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9075 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-23vboot2: read secdata and nvdataDaisuke Nojiri
This code ports antirollback module and tpm library from platform/vboot_reference. names are modified to conform to coreboot's style. The rollback_index module is split in a bottom half and top half. The top half contains generic code which hides the underlying storage implementation. The bottom half implements the storage abstraction. With this change, the bottom half is moved to coreboot, while the top half stays in vboot_reference. TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link. BUG=none Branch=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e Original-Reviewed-on: https://chromium-review.googlesource.com/206065 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org> (cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0) Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-20verstage should include the CBFS SPI wrapper, when configuredVadim Bendebury
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER configuration option enabled, so the verstage is missing the relevant files in some Makefiles. This patch fixes the problem. BRANCH=none BUG=none TEST=with the rest of the patches applied cosmos target builds fine with COMMON_CBFS_SPI_WRAPPER enabled Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579 Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8772 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: Add GigaDevice GD25LQ64C/GD25LB64C SPI ROM supportMarc Jones
GD25LQ64C and GD25LB64C have the same ID and settings. BUG=chrome-os-partner:25907 BRANCH=baytrail TEST=Boot with GD25LQ64 and check MRC data save/restore works. Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193238 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8770 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: do not use malloc in Gigadevice driverDavid Hendricks
This allows us to use the driver before ramstage. BRANCH=none BUG=none TEST=built and booted on Pinky Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa Original-Reviewed-on: https://chromium-review.googlesource.com/235864 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8774 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20spi: do not use malloc in Winbond driverVadim Bendebury
When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi_flash: add support for S25FL116KDaisuke Nojiri
S25FL116K family uses the first 3 bytes in response to a legacy identification command (9f) while previously supported models use the last 4 bytes. This change defines identify functions to allow both types to be handled correctly. BUG=none BRANCH=tot TEST=verified romstage is loaded on cosmos development board. Change-Id: I1970a9af17e81299fada5029724d405de4022156 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71 Original-Reviewed-on: https://chromium-review.googlesource.com/234431 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17elog: Fix compilation with CONFIG_CHROMEOS enabledStefan Reinauer
On ChromeOS devices the ELOG section size and offset are provided by the FMAP, rather than KConfig. Some upstream refactoring broke compilation in that case. Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-14OxPCIe952: Fix read8/write8 argumentKyösti Mälkki
This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-26drivers/i2c/w83793: Use devicetree.cb to set additional valuesTimothy Pearson
This allows devicetree.cb to set: Minimum PWM values Temperature sensor source Voltage sensor high/low limits Fan pin routing Default PWM values Manual PWM values per-fan Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8502 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-24drivers/intel/i210: Add new driver for Intel i210 MACPHYWerner Zeh
Add a new driver for Intel i210 MACPHY with the goal to update the MAC address in i210 if it is found during PCI scan. Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8404 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/xgi: Avoid double-freePatrick Georgi
xgifb_probe() doesn't own the object it tries to free in its error code path, potentially leading to a double-free in xgi_z9s_init(). Since we don't actually implement free, it doesn't matter too much, but let's keep things proper. Change-Id: I70c8f395fd59584664040ca6e07be56e046c80fc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8506 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/xgi: terminate file with newlinePatrick Georgi
That's just how we roll. Change-Id: I47ef62476703fdf2544d9cd77c30ae12452afeae Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23drivers/pc80/mc146818rtc: Enable RTC reset on power lossWerner Zeh
If function cmos_init() was called with parameter invalid set, this indicates, that the caller has found a power loss event in the RTC registers. In this case, we need to load the default date and time because it can be corrupted. Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8373 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/i2c/w83793: Remove incorrect zeroing of PWM valuesTimothy Pearson
Fan 2 and Fan 3 were inexplicably set to zero after device setup. Change-Id: I37945745dbfaf33eb28808d85cdf75dca401e44b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8520 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-20drivers/xpowers/axp209: Adapt to new I²C APIAlexandru Gagniuc
Originally, axp209_(read|write) accessors relied on i2c_(read|write) to return the number of bytes transferred. This was changed in * cdb61a6 i2c: Replace the i2c API. to return an error code or 0 on success. This caused the AXP209 check to fail. Fix the accessors to account for this new behavior. Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-02-16nvram: Add option to reset NVRAM to default parameters on every bootTimothy Pearson
In specific configurations, such as homogeneous supercomputing systems, changeable NVRAM parameters are more of a liability than a useful tool. This patch allows a coreboot image to be compiled that will always set the NVRAM parameters to their default values, reducing maintainance overhead on large clusters. Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8446 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14drivers/xpowers/axp209: Print a message when probing failsAlexandru Gagniuc
Probing is done by reading the ID register and comparing it to a known value. When there is a mismatch, print an error. Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-13Fix source code permissionsStefan Reinauer
Two source files were accidently marked executable. Switch them back to mode 644 (rw-r---r--) Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9 Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8426 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-12drivers/xgi: Fix user-visible typo in printkTimothy Pearson
Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-09fsp_baytrail: Get FSP reserved memory from the FSP HOB listMartin Roth
Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8308 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-06drivers/pc80/mc146818rtc: Reduce superfluous preprocessor useAlexandru Gagniuc
cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8306 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06drivers/xgi: Fix legacy VGA text mode initializationTimothy Pearson
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8360 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05drivers/xgi/z9s: Port Linux framebuffer initialization to corebootTimothy Pearson
Add native XGI Z9s framebuffer support to coreboot XGI initialization code largely taken from Linux 3.18.5 TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS with SeaVGABIOS enabled. Text appeared correctly on screen and interaction with graphical comboot menu was successful. However, Linux cleared the framebuffer on boot, rendering the screen useless until Linux loaded its native xgifb driver. Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-31FSP platforms: Clear area in CAR for cbmemMartin Roth
This patch clears the CAR area. The FSP loads the entire CAR area with a pattern instead of clearing it. At least the cbmem area needs to be cleared or cbmem will not use it. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8195 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-29drivers/intel/fsp: Add find_saved_temp_mem()Martin Roth
Add a function to retrieve the location of the CAR temporary memory that was saved by the FSP into the HOB structure. Change-Id: I2635de5207cd699740721d333a7706425b837651 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8194 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27drivers/intel/fsp: Add HOB tools to work with GUIDsMartin Roth
Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16coreboot tpm: Fix printk format specifiersFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I828776724dce287d9a7eb732f2c9ecccf8d68229 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209336 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b50c9441ddaeabc5aa039f2141853ed7ba7a9d5b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6e81312609448c531345e592ee371ea53dc0916c Reviewed-on: http://review.coreboot.org/8221 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-01-15drivers/i2c/w83795: Fix tautology from wrong return typeEdward O'Callaghan
The correct type-signature of 'do_smbus_write_byte' is: int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) and so storing the return type in a 'u32' is inappropriate, leading to a tautological compare of 'ret < 0' and 'err < 0'. Change-Id: I65486df7156c70af84fa00c336142d9a45998620 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8209 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-09elog: Add ELOG_TYPE_BOOT event using fake boot count if necessaryDavid Hendricks
This makes it so that we always log the generic "system boot" event. If boot count support has not been implemented, fake it. BUG=chrome-os-partner:28772 BRANCH=nyan TEST=booted on Big, ran "mosys eventlog list" and saw "System boot" event logged with boot count == 0 Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204525 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351 Reviewed-on: http://review.coreboot.org/8142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09spi: Add Spansion flash S25FL128PVadim Bendebury
Storm devices use more recent Spansion flash, add its description to the table of supported devices. BUG=chrome-os-partner:29871 TEST=the updated firmware boots all the way to depthcharge Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205182 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f Reviewed-on: http://review.coreboot.org/8146 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-06Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki
This reverts commit 9270553fff23462fcb298f154296319bf3639d15. Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8138 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06doxygen fixes: change @var to @param varMartin Roth
These files were trying to document the parameters, but didn't have the syntax quite right. Change the comments from @varname to @param varname as required by doxygen. Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8100 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06drivers/intel/fsp: split the UEFI HOB functions into hob.cMartin Roth
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting and passing information to coreboot. These seem to me like they should be in their own file, so I'm splitting them out of fsp_util.c. I'll be adding a couple more functions in the next patch. These functions should all be compliant to the Hand Off Block spec. Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8065 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06Re-factor 'to_flash_offset()' into 'spi_flash.h'Edward O'Callaghan
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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