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2019-09-09drivers/intel/fsp2_0: Fix minor whitespaceMarshall Dawson
Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35265 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACKKyösti Mälkki
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is confusing. Previously the region was shared for heap and stack, starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs. Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of stack guards and reduces amount of reserved CAR for bootblock and verstage, as the new allocation in .bss is only taken in romstage. BUG=b:140268415 Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-04drivers/spi/spi_flash.c: Add SPI vendor IDsRichard Spiegel
Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use it at spi_flash.c BUG=b:136595978 TEST=Build test of several platforms that don't use stoneyridge. Build and boot grunt (using stoneyridge new fch_spi). Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-02drivers/vpd: add framework to search VPD in romstageJonathan Zhang
Summary: Added a framework to search VPD in romstage before memory is avilable. vpd_cbmem.c and vpd_premem.c are added for code specific for premem environment and for environment that cbmem can be used. Since global variable is forbidden in romstage. A CAR_GLOBAL variable is defined in vpd.c. This variable holds VPD binary blobs' base address and size from memory mapped flash. The overall flow is: * The CAR variable g_vpd_blob is initialized if it was not, either at romstage (before FSP-M execution in case of FSP UPD customization), or at ramstage. * At ramstage, during CBMEM_INIT, the VPD binary blob contents are copied into CBMEM. * At vpd_find() which may be called at romstage or at ramstage, it sets storage for a local struct vpd_blob variable. * The variable gets contents duplicated from g_vpd_blob, if vpd_find() is called at romstage. * The variable gets contents obtained from CBMEM, if vpd_find() is called at ramstage. Added a call vpd_get_bool(). Given a key/value pair in VPD binary blob, and name of a bool type variable, set the variable value if there is a match. Several checks are in place: * The key/value length needs to be correct. * The key name needs to match. * THe value is either '1' or '0'. Test Plan: * Build an OCP MonoLake coreboot image, flash and run. Tags: Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-02drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacingPatrick Rudolph
Advertise the register spacing used by the BMC as set by the Kconfig. Tested on OCP Monolake. Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23soc/intel/cometlake: Add ISH Device IDBernardo Perez Priego
This Device ID is specific to CML, since it is obtained by reading ISH configuration RO register. In order to export ISH to kernel PCI device tree, this number must be included in list of devices supported. Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessorKyösti Mälkki
Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20AGESA,binaryPI: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-19intel/fsp2_0: Add TS_BEFORE_RAMINIT and TS_AFTER_RAMINITKyösti Mälkki
Change-Id: I99dbef5d52e4fc6cde22876216052cbe998822cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-15drivers/ipmi: make IPMI KCS status and command register spacing configurableJohnny Lin
The default is 1 (byte) spacing. Tested on Mono Lake with 4 (32-bit) spacing Change-Id: I47412c32e6db8f58b4fde8150adcbce349ca18a7 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-13drivers/i2c/generic: Add "compatible" property to _DSDFurquan Shaikh
This change adds support for allowing devices to provide a "compatible" property string that can be used when _HID is set to PRP00001. This is used to allow Linux kernel drivers to match the device to appropriate driver based on the OF-style compatible string. Reference: https://www.kernel.org/doc/Documentation/acpi/enumeration.txt BUG=b:129162037 TEST=Verified that atmel touchscreen gets enumerated correctly on kohaku using PRP0001 and compatible string. Change-Id: I8a306854c67ab2f056ea8774df46599ef0c55761 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08drivers/ipmi: Add option to wait for BMCPatrick Rudolph
The BMC on Supermicro X11SSH takes 34 seconds to start the IPMI KCS, but the default timeout of the IPMI KCS code is just 100 msec. Add a configurable timeout option to wait for the BMC to become ready. As it only should boot very long after power on reset, it's not a problem on reset or warm boot. Tested on Supermicro X11SSH. The IPMI driver doesn't fail with a time-out any more. Change-Id: I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/intel: Obsolete mmap_region_granularity()Kyösti Mälkki
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-06drivers/crb: Add support for PTTChristian Walter
When we use Intel Platform Trust Technologies, we need to verify that the enable bit is set before we use the integrated TPM. Change-Id: I3b262a5d5253648fb96fb1fd9ba3995f92755bb1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-06security/vboot: Add Support for Intel PTTChristian Walter
Add support for Intel PTT. For supporting Intel PTT we need to disable read and write access to the TPM NVRAM during the bootblock. TPM NVRAM will only be available once the DRAM is initialized. To circumvent this, we mock secdata if HAVE_INTEL_PTT is set. The underlying problem is, that the iTPM only supports a stripped down instruction set while the Intel ME is not fully booted up. Details can be found in Intel document number 571993 - Paragraph 2.10. Change-Id: I08c9a839f53f96506be5fb68f7c1ed5bf6692505 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-05drivers/intel/gma: Export Read_EDID() to CNico Huber
Change-Id: Icf802904c569e621ca3b3105b6107936776c5cee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31458 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05drivers/xpowers/axp209: Remove codeArthur Heymans
This code was only used by allwinner CPUs which is removed at this point. Change-Id: I31a2a502bffdc605cc31127723ed769b8665c314 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05drivers/intel/gma: Enable Kabylake+ libgfxinit supportNico Huber
Kaby, Coffee and Whiskey Lake are all supported by the same code path in libgfxinit. TEST=Played Tint on clevo/kbl-u(n130bu). Change-Id: Ic911bda3dd62c4d37a1b74a87fb51adc6c9d6ad4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31464 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-04drivers/fsp1_1/raminit: fix use of mrc_hobMatt DeVillier
Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs] inadvertently made use of the mrc_hob conditional on CONFIG_DISPLAY_HOBS, when there is no relation between the two, leading to MRC cache data being corrupted. On some devices this caused RAM training to be redone, on others it resulted in a bricked device. Fix this by removing the condition on CONFIG_DISPLAY_HOBS. Test: boot google/{cyan,edgar}, observe third boot and onward do not brick device, properly use mrc_hob via cbmem console and timestamps. Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31drivers/crb: Add CRB driver for TPM2 supportChristian Walter
Add the Command Response Buffer which is defined in the TPM 2.0 Specs. CRB can be specified with MAINBOARD_HAS_CRB_TPM, even though it is actually SoC/SB specific. Change-Id: I477e45963fe3cdbc02cda9ae99c19142747e4b46 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-31src/drivers/intel/ptt: Add PTT SupportChristian Walter
Add function which checks if Intel Platform Trust Technology / Intel integrated TPM is enabled/active. Change-Id: If93bb5e1a3a59b5045f4e44359683876fb387a71 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34380 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23include/spi-generic: Append unit to macro namesUwe Poeche
This patch appends a unit (milliseconds) to time-out macro names for better understanding the code which is using the macros. Change-Id: Ibc4beda2660a83fd5f0ed325b2ee3148c6d96639 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34384 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23include/spi-generic: move common flash timeoutsUwe Poeche
This patch moves SPI_FLASH time-outs from spi/spi_flash_internal.h for SPI SW-sequencing to include/spi-generic.h to provide also for SPI HW-sequencing. tested on siemens/bdx1 and checked if all includes of spi_flash_internal.h on other places provide an include of spi-generic.h before Change-Id: I837f1a027b836996bc42389bdf7dbab7f0e9db09 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-19drivers/i2c/dw: Don't try to generate unselected speeds in ACPI tableTim Wawrzynczak
When generating entries in SSDT for DesignWare I2C controllers, only use the speed selected in the devicetree, instead of trying all of them. This quiets a message which looks like a bug ("dw_i2c: bad counts"), later on in this driver when checking rise/fall times. BUG=b:137298661 BRANCH=none TEST=Boot and verify that I2C controllers still function, and the nastygram message is gone. Change-Id: I07207ec95652e8af1a42bfe31214f61a183a134e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34385 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15src: Use '#include <timestamp.h>' when neededElyes HAOUAS
Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13drivers/intel/wifi: Make Intel wifi driver arch agnosticKarthikeyan Ramasubramanian
Mark Intel WiFi driver to depend on PCI and remove the dependency on x86 architecture. BUG=None BRANCH=None TEST=Compile and Boot to ChromeOS. Change-Id: I762007d53b43bbc78924ee8efe236d6a7ff4dc57 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33959 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13drivers/wifi: Add generic WiFi driverKarthikeyan Ramasubramanian
Add generic WiFi driver to support common device operations across multiple types of WiFi controller. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables and wakeup GPE information. Ensure that the SSDT table is same after the change. Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-13soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13drivers/elog: Fix ELOG_GSMI dependencyKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG only, while HAVE_SMI_HANDLER currently tells if SMM will be installed. Move rest of the file under same 'if ELOG' block. Change-Id: I620d3ce5aa9632d862d6480922144f002cf6423b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34195 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10drivers/intel/fsp1_1/raminit.c: Always check FSP HOBsFrans Hendriks
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS. Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs. Use BIOS_ERR of printk() for FSP errors. BUG=N/A TEST=Check console output on Facebook FBG1701. Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-09drivers/intel: Move FSP stage_cache implementation into common blockSubrata Banik
Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-08drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2Kyösti Mälkki
No longer fallback to UDELAY_IO as default. Since these are not cpu properties or features, move the Kconfig location. Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-07drivers/amd/agesa: Drop redundant stack allocationKyösti Mälkki
The removed call was there to support case LATE_CBMEM_INIT=y, HAVE_ACPI_RESUME=y. Same stack space is already allocated with postcar_frame_init() call. Change-Id: I03a44bc3252f553b1769d362b2f442d3e6ab73f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-04device/pci_ops: Define pci_find_capability() just onceKyösti Mälkki
Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-04drivers/intel/fsp1_1: Adjust postcar MTRRsKyösti Mälkki
Use of romstage_ram_stack_bottom() was invalid, it potentially uses a different ROMSTAGE_RAM_STACK_SIZE from the postcar_frame_init() call. If alignment evaluated to 1 MiB, that WB MTRR may not have covered all of CBMEM range, having some impact on boot speeds. There is no need to accurately describe write-back MTRR ranges for postcar. Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 01:19:14 +0000