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2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24drives/i2c/designware: incorporate device_operations supportAaron Durbin
In ramstage the device_operations are needed for the i2c designware host controller. Move the intel/common/block/i2c implementation into the generic driver so other platforms can take advantage of it. BUG=b:72121803 Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24device/i2c_bus: allow i2c_bus and i2c_simple to coexistAaron Durbin
If one wants to implement both i2c_bus.h and i2c_simple.h APIs the compilation unit needs to be guarded or coordinated carefully with different compilation units. Instead, name the i2c_bus functions with _dev such that it indicates that they operate on struct device. One other change to allow i2c_bus.h to be built in non-ramstage environments is to ensure DEVTREE_CONST is used for the dev field in struct bus. BUG=b:72121803 Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23drivers/i2c/max98373: Add driver for generating device in SSDTN, Harshapriya
Add a device driver to generate the device and required properties into the SSDT for max98373. TEST=verified SSDT contained relevant params BUG=None Change-Id: Id45f74e52855f4b19276e1d3d673d5448207ef4b Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/22673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22drivers/net: Add device index for multiple NIC cardsGaggery Tsai
This patch adds a member device_index to r8168 chip information which allows driver to identify which NIC card requests MAC address. In this implementation, only 10 NIC cards are supported, the device index is in the range of 0 to 10. Regarding to MAC address mapping, when there is only one NIC on DUT, it is treated as a special case mapping to "ethernet_mac" in VPD for backward compatibility. When there are multiple NICs on DUT, they are mapping to "ethernet_macN" where N is [0-9]. Device tree configuration: For single NIC: .device_index = "0", maps to "ethernet_mac" For multiple NICs: .device_index = "[1-10]", maps to "ethernet_mac[device_index - 1]" BUG=b:69950854 BRANCH=None TEST=Added device_index = [0-10] under /drivers/net in device tree && Programmed the mac address to VPD in shell vpd -s ethernet_mac=<mac address> or vpd -s ethernet-mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-20drivers/mrc_cache: Always generate an FMAP regionArthur Heymans
This automatically generates an FMAP region for the MRC_CACHE driver which is easier to handle than a cbfsfile. Adds some spaces and more comments to Makefile.inc to improve readability. Tested on Thinkpad x200 with some proof of concept patches. Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-19drivers/mrc_cache: Make bootstate for SPI writes variableMarshall Dawson
The default time for writing MRC data to flash is at the exit of BS_DEV_ENUMERATE but this is too early for some implementations. Add an option to Kconfig for allowing a late option to be selected. The timing of the late option is at the entry of BS_OS_RESUME_CHECK. TEST=Select option and inspect console log on Kahlee BUG=b:69614064 Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22937 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19drivers/amd/agesa: Fix AGESA heap deallocatorMarc Jones
Ported from commit e6033ce1 soc/amd/common/block/pi: Fix AGESA heap deallocator The deallocation was always subtracting the header, even when it shouldn't. This caused problems for the allocator where buffer sizes were incorrect and freed and used buffers could collide. Fix the deallocation size. Clear deallocated concatinated buffer header memory. Fix the initial calculation of the total buffer size available to be allocated. Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36 Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-11intel/fsp2_0: Set boot mode default as per s3wake statusAamir Bohra
Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data validity. With current implementation in S3 resume path, if mrc cache data is invalid, the bootmode is not updated further and remains set at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get incorrect boot mode context and reinitialize memory in S3 resume path. In correct flow fspm should have correct bootmode context i.e. S3 resume and return error in case mrc cache data is invalid or not found. BUG=b:70973961 BRANCH=None TEST=Verify correct bootmode is set on S3 resume, even when mrc cache data is invalid. Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/23156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-11intel/fsp2_0: Issue hard reset in S3 resume for invalid mrc cache dataAamir Bohra
In S3 resume, for cases if valid mrc cache data is not found or RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION. This gets memory to be retrained in S3 flow. Data context including that of imdr root pointer would be lost, invoking a hard reset in romstage post memory init. Issuing hard reset before memory init, saves fsp memory initialization and training overhead. BUG=b:70973961 BRANCH=None TEST=Verify S3 resume flows on soraka. Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-24drivers/mrc_cache: Make CACHE_MRC_SETTINGS not selectableArthur Heymans
Don't allow the user to select this manually, since it doesn't build on platforms that don't use it. Don't set the bool value so that it doesn't show as not selected in the .config file of platforms that don't use this. Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20drvs/lenovo/hybrid_graphics/romstage: Fix dGPU activationPatrick Rudolph
While the older boards use a GPIO that has no state, the newer boards' PMH7 does have a state, that even remains after reboot. Don't assume default values in PMH7 and instead always program it. Fixes dGPU doesn't show up when switching from integrated to discrete GPU. The workaround of removing all power is no longer necessary. Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19drivers/mrc_cache: only add mrc.cache when CACHE_MRC_SETTINGS is setIru Cai
In commit decd0628 (drivers/mrc_cache: move mrc_cache support to drivers) mrc.cache is always added, but CONFIG_MRC_SETTINGS_CACHE_SIZE is not used in Sandy Bridge, which makes mrc.cache have zero size and the machine will fail to boot after the first boot. Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-18spi/tpm: Clear pending irqs during tpm2_initShelley Chen
Seeing some instances were cr50 spi driver is starting a new transaction without getting a ready interrupt from cr50, which means that there are pending interrupts. Clearing these to be sure there are not any stale irqs for the next transaction. BUG=b:69567837 BRANCH=None TEST=run FAFT and see if any 0x2b recovery boots occur Change-Id: Ie099da9f2b3c4da417648ae10a5ba356b7a093ff Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17drivers/mrc_cache: move mrc_cache support to driversAaron Durbin
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-15drivers/spi/spi_flash: add flash region protection to controllerAaron Durbin
Provide a spi controller specific protection callback to take advantage of special spi flash controllers that have internal protection registers built into the implementation. It's an optional callback for spi controllers. BUG=b:69614064 Change-Id: Ie50a6ce3bbda32620a25dd26fda1af944940bf28 Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-14drivers/spi: Enable flashconsole in verstageDuncan Laurie
Enable the flashconsole driver in verstage so it can be used with VBOOT enabled. This was tested on a VBOOT enabled system using flashconsole to store the boot log. Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14drivers/pc80/tpm: Remove unused ACPI opregionDuncan Laurie
The opregion and fields are left over from when ACPI ASL code was reading registers to determine the current setup. Now that the ACPI device is generated with the correct information already this code is not used at all and can be removed from the tree. Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22854 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12drivers/intel/gma: Power up legacy VGA block earlyNico Huber
This is required at least on Skylake to be able to configure text mode. 3rdparty/libgfxinit is also updated by the single commit: 42fb2d065d gma: Add procedure to power up legacy VGA block Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28spi/tpm.c do not waste time on wake pulses unless necessaryVadim Bendebury
The Cr50 secure chip implementation is guaranteed not to fall asleep for 1 second after any SPI slave activity. Let's not waste time on the wake up ping when it is not necessary. BRANCH=cr50 BUG=b:68012381 TEST=using a protocol analyzer verified that the wake pulses are generated only when the new coreboot stage or depthcharge start, not on every SPI slave transaction. Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-27drivers/net: add SSDT ACPI declaration and WOL featureGaggery Tsai
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and also _PRW for WOL feature. Besides, adds a wake variable in chip information. BUG=b:69290148 BRANCH=None TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168 chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW are filled correctly && put system into S3 && sudo etherwake -i eth0 $MAC to make sure the system could be woken up by WOL package. Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22drivers/i2c/tpm/cr50: Simplify and increase init delay to 30 secondsDuncan Laurie
The Cr50 i2c driver provides separate entry points for probing and initialization, but probing function does not really do much. It also claims and releases locality on every coreboot stage, but there is no need for this - locality should be definitely claimed after reset and then it could be retained through the boot process. On top of that the driver does not properly account for long time it could take the Cr50 chip to come around to reset processing if TPM reset request was posted during a lengthy TPM operation. This patch addresses the issues as follows: - tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept around to conform to the expected driver API. - tpm_vendor_init() invokes a function to process TPM reset only in the first stage using TPM (typically verstage), the function checks if locality is claimed and if so - waits for it to be released, which indicates that TPM reset processing is over. - before claiming locality check if it is already taken, and if so - just proceed. BRANCH=none BUG=b:65867313, b:68729265 TEST=Verified that reef no longer hangs during EC reboot and firmware_Cr50ClearTPMOwner (not yet merged) tests. Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21spi/tpm: claim locality just once during bootVadim Bendebury
All coreboot stages using TPM start with the same sequence: check if locality is claimed, if so, release it by writing 'active locality' bit, then try claiming it. This is actually not a proper procedure: section "5.5.2.3.1 Command Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification Level 00 Revision 00.430 Family 2" lists overwriting active locality status bit as a means of triggering TPM command abort. On top of that, none of the coreboot stages releases locality, it is enough to claim it once when device starts booting. In fact, locality being active when the device is in verstage is most likely due to delayed TPM reset processing by the Cr50 TPM: reset is an asynchronous event, and is processed once current command processing completes. The proper procedure is to wait if locality is active until it is released (which will happen when Cr50 processes reset) and then proceed to claim it. This needs to happen only during verstage, other stages using TPM are guaranteed has been claimed earlier. BRANCH=gru BUG=b:65867313 TEST=the new autotest triggering EC reset during key generation process does not cause boot failures on Fizz device any more. Below are times verstage had to wait: TPM ready after 3132 ms TPM ready after 22120 ms TPM ready after 4936 ms TPM ready after 6445 ms TPM ready after 11798 ms TPM ready after 27421 ms TPM ready after 4582 ms TPM ready after 7532 ms TPM ready after 27920 ms TPM ready after 3539 ms TPM ready after 12557 ms TPM ready after 6773 ms TPM ready after 1631 ms TPM ready after 197 ms TPM ready after 24330 ms TPM ready after 3241 ms Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-16drivers/spi/tpm: Poll TPM_VALID bit until validShelley Chen
In case the TPM is doing a long crypto operation the initial probe could be very delayed. Rather than end up in recovery make the delay long enough to accommodate the (current) long crypto times. This would add a maximum of 30 seconds to boot time. Mirroring changes done on i2c side in CL:756918 BUG=b:65867313, b:68729265 BRANCH=None TEST=Make sure fizz boots up Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09drivers/i2c/tpm/cr50: Increase init delay to 30 secondsDuncan Laurie
In case the TPM is doing a long crypto operation the initial probe could be very delayed. Rather than end up in recovery make the delay long enough to accommodate the (current) long crypto times. BUG=b:65867313, b:68729265 TEST=Verified that Soraka no longer hangs during EC reboot test. Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-03siemens/nc_fpga: Set FW_DONE bit before jumping to payloadWerner Zeh
Once coreboot is ready and payload has been loaded a bit inside the NC FPGA needs to be set to notify this event. As there are NC FPGAs with different PCI device IDs save the BAR0 address in a global variable once the driver evaluates this address. It can then be used to access the register from the boot state machine callback without the need of searching for all possible PCI devices again. As this driver is only used at ramstage there is no need of using CAR_GLOBAL for the global variable. Use a Kconfig switch to make this feature selectable from mainboard as not every mainboard may have a FPGA with that capability. Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03drivers/intel/fsp2_0/hob_verify: Correct conversion specifierPaul Menzel
Use the correct conversion specifier for `size_t` to fix the error below. ``` src/drivers/intel/fsp2_0/hob_verify.c:31:4: error: format '%lx' expects \ argument of type 'long unsigned int', but argument 4 has type \ 'size_t {aka unsigned int}' [-Werror=format=] "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", ^ range_entry_size(&tolum), cbmem_overhead_size()); ~~~~~~~~~~~~~~~~~~~~~ ``` Found-by: gcc (Debian 7.2.0-8) 7.2.0 Change-Id: I4631672211095f9934925e9bd230ccbf63c736af Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-01spi/tpm: Make sure AP properly syncs up with Cr50Vadim Bendebury
When Cr50 TPM is being reset, it continues replying to the SPI bus requests, sends wrong register values in response to read requests. This patch makes sure that the TPM driver does not proceed unless proper value is read from the TPM device identification register. If the read value is still wrong after 10 retries taken with 10 ms intervals, the driver gives up and declares TPM broken/unavailable. BRANCH=cr50 BUG=b:68012381 TEST=ran a script resetting the Fizz device as soon as the "index 0x1007 return code 0" string shows up in the AP console output. The script keeps rebooting the Fizz indefinitely, before this script Fizz would fail to read TPM properly and fall into recovery after no more than four reboots. Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01drivers/net/r8168: Add customized LED modeGaggery Tsai
This patch adds a function to program a customized LED setting for Realtek 81xx family. It reads the settings from devicetree under target board and programs the setting to offset 0x18 and 0x19. BUG=b:65437780 TEST=Add customized_leds register in devicetree.cb under target board, enable RT8168_SET_LED_MODE flag. Make sure the setting is programmed correctly to offset 0x18 and 0x19. Observed the LEDs were behaving as expected. Executed suspend/resume and the LEDs were still working as expected. Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber
The current header `i915.h` is too invasive to be used everywhere where we want to use *libgfxinit*. Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-23drv/intel/gma/opregion: fix opregion version for WindowsMatt DeVillier
Although Intel's current spec[1] shows the OpRegion structure version as being the top 16 bits of the field, Intel's Windows drivers require the OpRegion structure version to be in the top 8 bits of the field when not using a VGA BIOS (eg, NGI or GOP driver). As the Linux i915 driver only checks that the version is >= 2, there is no change in functionality there. This change effectively matches Intel's implementation in TianoCore, where the version is set to 0x0200 << 16. [1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and Legacy mode with libgfxinit, observe Intel GPU driver functional. Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22intel/i210: Set bus master bit in command registerWerner Zeh
There are still Ethernet drivers out there in the wild which expect that the master enable bit was set by firmware. A missing master enable bit will lead to a non-functional driver. Though it is clear the task of the driver to set this bit it is too late now. So work around this issue on firmware level...again! Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-19elog: Support logging S0ix sleep/wake info in elogFurquan Shaikh
1. Add support for new GSMI commands to log S0ix entry/exit information in elog. 2. In case of resume, provide callbacks to allow platform and mainboard to log any wake source information. BUG=b:67874513 Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16drivers/elog: Fix debug build errorsJohn E. Kabat Jr
Add hexdump.c to Makefile.inc and change an elog_debug format to use %z for size_t arguments. This corrects build errors when ELOG_DEBUG is used. Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16console/flashconsole: Enable support for postcarYouness Alaoui
If FSP 2.0 is used, then postcar stage is used and the flashconsole as well as spi drivers needed to be added. Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16drivers/uart8250mem: Check for zero base addressMarshall Dawson
Before adding a new UART to the coreboot/lb table, verify that it has a non-zero base address. This is consistent with all other functions that use the uart_platform_base() function. This was tested on google/kahlee by using an invalid UART number and forcing the base address to 0. Execution was able to complete through depthcharge and into the OS. Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21996 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13drv/intel/gma/opregion: Add common init_idg_opregion()Matt DeVillier
Add a new common method to initialize ACPI OpRegion. * Try to locate vbt.bin in CBFS. * Try to locate VBIOS in CBFS. * Keep existing code to probe at 0xc0000. Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at 0xc0000. Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS). In all cases linux was successfully provided with VBT from ACPI opregion. Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-06soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbtPatrick Georgi
All callers of locate_vbt just care about the file content and immediately map the rdev for its content. Instead of repeating this in all call sites, move that code to locate_vbt. Change-Id: I5b518e6c959437bd8f393269db7955358a786719 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05drivers/intel/fsp2_0: use common code to fetch vbt.binPatrick Georgi
No need for having two of everything in the coreboot codebase. Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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