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2019-11-03cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-02cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80Kyösti Mälkki
Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src/[arch-lib]: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ibb7b48a7a144421aff29acbb7ac30968ae5fe5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/36329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27src/{device,drivers}: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27src: Use 'include <boot/coreboot_tables.h>' when appropriateElyes HAOUAS
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26drivers/intel/fsp2_0: move die() calls to the functionsMichael Niewöhner
Since there are no calls where we wouldn't die(), move die() calls into the fsp_find_* functions. Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-26drivers/intel/fsp1_1: remove orphaned functionalityMichael Niewöhner
Remove orphaned functionality from the FSP1.1 driver that only has been used by skylake, which is now FSP2.0-only. Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24drivers/ipmi: Add IPMI BMC FRB2 watchdog timer supportJohnny Lin
Add a function for initializing and starting FRB2 timer with the provided countdown and action values, and a stop function for stopping the timer. Tested on OCP Monolake. Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24drivers/i2c/rt1011: Add a driver for RT1011Cheng-Yi Chiang
RT1011 is a smart amplifier. It needs to know speaker related parameters including speaker resistor value and temperature when the calibration is done in order to run Dynamic Speaker Management (DSM) algorithm on chip. The purpose of DSM is to protect speaker when the volume is large. The calibration data of speaker is stored in VPD in factory. This driver is needed to read data from VPD and write to ACPI _DSD when config CHROMEOS_DSM_CALIB is turned on. Kernel rt1011 codec driver will read these device properties to set up codec accordingly on boot. The reason to prepare these parameters in coreboot is because kernel codec driver expects to read per-device parameters directly from device properties. Another benefit is that other OS can also take these parameters through ACPI _DSD table and take benefit of DSM on RT1011. The kernel driver device properties of RT1011 are documented at linux/Documentation/devicetree/bindings/sound/rt1011.txt It is currently in ASoC maintainer's tree at https://kernel.googlesource.com/pub/scm/linux/kernel/git/broonie/sound/+/for-next/ and hopefully should be merged to mainline kernel in the next merge window. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-23drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_optionArthur Heymans
Avoid searching for cmos_layout.bin each time get/set_option is called on platforms with NO_CAR_GLOBAL_MIGRATION. Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-22AUTHORS: Move src/drivers/[l*-v*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-22AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-21drivers/intel/fsp2_0: Add ENV_CACHE_AS_RAM check for consumed rangesMarshall Dawson
Rename the freeranges array to better match what they represent, i.e. ranges that are used by the current running program and CAR region that is not unallocated. Skip adding the CAR region if cache-as-RAM is not active. Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'Elyes HAOUAS
Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20drivers/intel/fsp2_0: Make vbt_get() conditionalMarshall Dawson
Skip calling vbt_get() if FSP is not supposed to run GOP. Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-18src: Remove unused include '<device/pci_ids.h>'Elyes HAOUAS
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18build: Mark bootblock files on x86 as IBBPatrick Rudolph
* Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-16drivers/usb: Enable EHCI debug during verstageArthur Heymans
Change-Id: I14843c1944f2c1e0a26870b576bac549c0cac7f9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-09drivers/spi: ignore -Wvla on clang tooGreg V
Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-08device/root_device: Consolidate common _scan_bus() functionsNico Huber
scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04devicetree: Fix improper use of chip_operationsKyösti Mälkki
Auto-discoverable PCI devices do not require field .enable_dev of chip_operations to be set. They are matched with PCI drivers by the use of PCI vendor and device ID fields. The name given for the chip_operations struct must match the pathname the way it is present in the devicetree.cb files. If there was no match, util/sconfig would currently choose to use the empty weak declaration it creates in static.c file. Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-30drivers/i2c/lm96000: Add more settings for fan controlNico Huber
Allow to set a lower temperature limit, as the currently hard-coded 25C may be to low for a given temperature sensor. Also enable smoo- thing, currently hard-coded to the maximum interval of 35s, and set the hysteresis value. Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30drivers/i2c/lm96000: Fix integer sign issueNico Huber
We accidentally converted an `int` return value to an `unsigned`, making it impossible to check for errors with `< 0`. Fix that by using an `int` variable. Change-Id: I5433c27e334bc177913e138df83118b128c674b7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30drivers/i2c/at24rf08c: Add proper Kconfig optionNico Huber
The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend on VENDOR_LENOVO. Thus, it couldn't be selected by boards from other vendors. So we add another Kconfig that selects it here. NB. It's still unclear how the two drivers in this directory are related (at24rf08c and lenovo_serial). From the code, it doesn't look like the latter belongs here. Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30device,drivers/: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-28usbdebug: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
We can always PCI config accessors with pci_devfn_t. Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Note that the code assumes mainboard code to configure any PCI bridges prior to calling console_init(). Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-21drivers/wifi/generic.c: Upper case the AML WiFi name as required by specAndrew McRae
ACPI 6.3, ASL 20.2.2 (Name Objects Encoding) states: LeadNameChar := 'A'-'Z' | '_' NameChar := DigitChar | LeadNameChar Hence, the Intel WiFi names generated in ASL are required to be upper-cased letters. BUG=b:141206986 TEST=Reflash and confirmed SSDT table has correct name. Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc Signed-off-by: Andrew McRae <amcrae@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35466 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15{cpu,device,drivers}: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13drivers/pc80: Remove some __PRE_RAM__ and __SMM__Kyösti Mälkki
Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13drivers/intel/fsp2_0: Allocate cfg_region_size for UPDMarshall Dawson
In FSP-S, the driver constructs its pointer to UPD using the offset in the header. Similarly, use the header's cfg_region_size for allocating memory and copying the default configuration. Add sanity checks for unexpedted configuration and UPD header conditions. TEST=Verify OK on Mandolin, verify a mock error condition BUG=b:140648081 Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13drivers/elog: Add elog_boot_notify()Kyösti Mälkki
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13intel/fsp2_0: Move TS_BEFORE_INITRAMKyösti Mälkki
Exclude FSP-M loading from the timestamps used for RAM detection and training process. Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-11intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE KconfigSubrata Banik
For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000. Refer to FSP integration guide to know the exact FSP requirement. BUG=b:140268415 TEST=Build and boot CML-Hatch and ICL. Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11src: Remove unneeded include <arch/interrupt.h>Elyes HAOUAS
Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-11arch/x86: Drop _car_relocatable_data symbolsKyösti Mälkki
These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-11arch/x86: Move ehci_dbg_info outside _car_relocatable_dataKyösti Mälkki
As code already used CBMEM hooks to switch from CAR to CBMEM it was never necessary to have the structure declared inside _car_relocatable_data. Switch to use car_[get|set]_ptr is mostly for consistency, but should also enable use of usbdebug with FSP1.0 romstage. Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-09drivers/intel/fsp2_0: Fix minor whitespaceMarshall Dawson
Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35265 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACKKyösti Mälkki
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is confusing. Previously the region was shared for heap and stack, starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs. Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of stack guards and reduces amount of reserved CAR for bootblock and verstage, as the new allocation in .bss is only taken in romstage. BUG=b:140268415 Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-04drivers/spi/spi_flash.c: Add SPI vendor IDsRichard Spiegel
Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use it at spi_flash.c BUG=b:136595978 TEST=Build test of several platforms that don't use stoneyridge. Build and boot grunt (using stoneyridge new fch_spi). Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-02drivers/vpd: add framework to search VPD in romstageJonathan Zhang
Summary: Added a framework to search VPD in romstage before memory is avilable. vpd_cbmem.c and vpd_premem.c are added for code specific for premem environment and for environment that cbmem can be used. Since global variable is forbidden in romstage. A CAR_GLOBAL variable is defined in vpd.c. This variable holds VPD binary blobs' base address and size from memory mapped flash. The overall flow is: * The CAR variable g_vpd_blob is initialized if it was not, either at romstage (before FSP-M execution in case of FSP UPD customization), or at ramstage. * At ramstage, during CBMEM_INIT, the VPD binary blob contents are copied into CBMEM. * At vpd_find() which may be called at romstage or at ramstage, it sets storage for a local struct vpd_blob variable. * The variable gets contents duplicated from g_vpd_blob, if vpd_find() is called at romstage. * The variable gets contents obtained from CBMEM, if vpd_find() is called at ramstage. Added a call vpd_get_bool(). Given a key/value pair in VPD binary blob, and name of a bool type variable, set the variable value if there is a match. Several checks are in place: * The key/value length needs to be correct. * The key name needs to match. * THe value is either '1' or '0'. Test Plan: * Build an OCP MonoLake coreboot image, flash and run. Tags: Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-02drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacingPatrick Rudolph
Advertise the register spacing used by the BMC as set by the Kconfig. Tested on OCP Monolake. Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23soc/intel/cometlake: Add ISH Device IDBernardo Perez Priego
This Device ID is specific to CML, since it is obtained by reading ISH configuration RO register. In order to export ISH to kernel PCI device tree, this number must be included in list of devices supported. Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessorKyösti Mälkki
Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20AGESA,binaryPI: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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