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2020-12-01ec/google/chromeec/acpi: Make OperationRegion brace alignSubrata Banik
Inject TAB to make OperationRegion closing brace align with opening brace. Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23ec/google/chromeec: set DPTC power parameter at OS startupKevin Chiu
set DPTC power parameter per clamshell/tablet mode after EC OP region is accessible. BUG=b:157943445 BRANCH=zork TEST=1. emerge-zork coreboot 2. power on DUT in tablet mode then check "thermctl_limit" will change automatically Change-Id: Ic3e1119881790c34f5649986334b4e3cecafc02b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17ec/google/chromeec: Add dptc interface supportChris Wang
add the dptc interface support when system in tablet mode. In some FP5/FT5 platform, which will have different power or thermal parameters depends on different form factor. BUG=b:157943445 BRANCH=Zork TEST=Build. check the setting changed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I2be7942132cea474237f531021ad4fd9856b5050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44265 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Drop codec.aslFurquan Shaikh
This change drops codec.asl file from Chrome EC since it is now unused. Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14ec/google/chromeec: Call \PNOT () on initializing AC power stateFurquan Shaikh
This change calls \PNOT () method when AC power state is initialized to allow platform code to take appropriate action. BUG=b:157752693 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27ec/google/chromeec/acpi/superio: Add PS/2 Mouse ACPI entryRaul E Rangel
The PNP ID Means: PNP0F13 PS/2 Port for PS/2-style Mice BUG=b:145575366 BRANCH=none TEST=Verified mouse was initialized Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a4f071ad54730ea75f75ebf1633a4a08f7f2dd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080664 Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Commit-Queue: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41639 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21ec/google/chromeec/acpi: Add CROS EC CODEC deviceYu-Hsuan Hsu
This is currently used by trembyle. Add it in a common location so other boards can use it. BUG=b:147200751 BRANCH=none TEST=Able to get ec codec on trembyle Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13google/chromeec: Add USB MUX InterruptBrandon Breitenstein
Kernel relies on the USB MUX interrupt to configure USB devices that are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt so the Kernel can properly receive and configure USB devices BUG=b:152902608 TEST=buld_packages for volteer and verified that Proto 1 and Proto 2 are now seeing extcon events Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Prashant Malani <pmalani@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-05src/ec: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14ec/google/chromeec/acpi: Move ECPD under CRECPrashant Malani
Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP device drivers can access the parent EC device to communicate with the EC. Also, update the Notify() call to reflect the new location of the ECPD device. Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-18soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarksWim Vervoorn
Prevent iasl remarks about unused parameters. BUG=N/A TEST=build Change-Id: I54fa4712e618038fdd5a96c2012c2ec64ca34706 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16ec/google/chromeec/acpi: move PS2K under PCI0Matt DeVillier
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too). Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms. Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10. Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24ec/google/chromeec/acpi: Drop wrong _ADR objectElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18ec/google/chromeec: Pass reference of object to BBST() methodDuncan Laurie
The BBST() method writes an updated status flag mask that is intended to be stored back in the battery object. This value needs to be passed as a reference to an object to prevent it from being evaluated at the time the method is loaded or it will not actually update the BSTP value in the battery device. This was tested by instrumenting the _BST method in the primary battery and ensuring the value can be updated by the BBST method. Change-Id: Ia8e207a2990059a60d96d8e0f3ed3c16a55c50f4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-11mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQEdward Hill
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. On this platform, interrupts are routed via the GPIO controller so need to be registered using GpioInt instead of Interrupt. BUG=b:123750725 BRANCH=grunt TEST=MKBP events still received (with matching EC and kernel changes) Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-15google/chromeec/acpi/ec: Add support for Device DPTF Profile NumberKarthikeyan Ramasubramanian
In order to support Multi-DPTF profile, Device DPTF Profile Number is introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset 0x09. This bit field stays along with Tablet Mode Device flag. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes(base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES since it aligns with the use-case. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes (base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-12ec/google/chromeec: Configure EC_SYNC_IRQ as level triggeredFurquan Shaikh
EC_SYNC_IRQ from EC to host is level-triggered in practice and configuring it as edge-triggered on the host results in host missing events if there are multiple events queued on the EC side. This is because Linux kernel driver reads one event per irq and the EC does not de-assert the interrupt line until all events are drained out. This results in event queue being filled up completely on the EC and the host failing to see any of those events. This change configures EC_SYNC_IRQ as level triggered to allow the host to read events from the the EC as long as the line is asserted. BUG=b:118949877 Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2018-11-06chromeec: Disable battery remaining capacity workaroundDaisuke Nojiri
If remaining charge is more than x% of the full capacity, the remaining charge is raised to the full capacity before it's reported to the rest of the system. Some batteries don't update full capacity timely or don't update it at all. On such systems, compensation is required to guarantee the remaining charge will be equal to the full capacity eventually. On some systems, Rohm charger generates audio noise when the battery is fully charged and AC is plugged. A workaround is to do charge- discharge cycles between 93 and 100%. On such systems, compensation was also applied to mask this cycle from users. This used to be done in ACPI, thus, all software components except EC was able to see the compensated charge. This patch is part of the effort of moving the logic to EC. With this and the EC changes, EC can see what the rest of the system sees, thus, can control LEDs synchronously (to the display percentage). Another rationale of this move is EC can perform more granular and precise compensation than ACPI since it has more knowledge about the battery and the charger. CQ-DEPEND=CL:1312204 BUG=b:109954565,b:80270446,chromium:899120 BRANCH=none TEST=Verify charge LED changes to white (full) on Sona synchronously to the display percentage. TEST=Verify charge LED changes to blinking white (low) on Sona within 30 seconds synchronously to the display percentage. Change-Id: I0b51911b90dc2e7fcf5c730c54d9fda1fea76aa9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/29441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-10-04ec/google/chromeec: Define a sync IRQ if neededDuncan Laurie
Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02chromeec: PS2K node can't be under SIO nodeStefan Reinauer
Some operating systems won't find the keyboard if it is under the SIO node. BRANCH=none BUG=none TEST=Boot Windows, observe that keyboard is working Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> Original-Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Original-Reviewed-on: https://chromium-review.googlesource.com/895364 Change-Id: If99e15bef2173c44cecaa8fdeaa69381bd0e499a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28eve: Specify a unique ID for PS2 devicesLucas Chen
Windows certification tests will fail if the PS2 devices are using Plug and Play ID (PNP0303). For all Chromebooks we should use GOOG000A. BRANCH=eve BUG=b:110066056 TEST=AltOS certification test verify. Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1098874 Reviewed-by: Matt Delco <delco@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23google/chromeec: Add support for "base attached switch" deviceDmitry Torokhov
On some detachables, the mere presence of attached base is not enough to determine whether the device is in tablet mode or not, so we introducing a new "switch" in EC, separate from "Tablet Mode" switch, to signal whether the base is attached or not. We also want the driver to be separate from cros_ec_keyb, so we create a new ACPI device, C(hrome)B(ase)A(ttached)S(witch), with HID GOOG000B, and guard it with EC_ENABLE_CBAS_DEVICE. Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28260 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17ec/google/chromeec: Fix ACPI FWTS errorMarc Jones
Fix the following FWTS error: FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line 3038 Line | AML source -------------------------------------------------------------------------------- 03035| Return (One) 03036| } 03037| 03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query | ^ | Warning 3115: Not all control paths return a value (_Q09) 03039| { 03040| If (Acquire (PATM, 0x03E8)) 03041| { ================================================================================ ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths do not return a value. All control paths that return must return a value otherwise unexpected behaviour may occur. This error occurs because a branch on an conditional op-code returns a value and another does not, which is inconsistent behaviour. _Q09 is a reserved method and can't return a value. Change the logic so that no return is used and avoid this test error. BUG=b:112476331 TEST=Run FWTS. Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-13ec/google/chromeec: de-dup a _UIDMatt Delco
There's two instances od _UID 1 for PNP0C02. This change moves the more system-specific instance of the two to a higher number. I believe these are the 4 I'm seeing. soc/intel/skylake/acpi/systemagent.asl Device (PDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) soc/intel/skylake/acpi/lpc.asl Device (LDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) ec/google/chromeec/acpi/superio.asl Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) ec/google/chromeec/acpi/superio.asl Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 3) Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-02ec/google/chromeec: Remove notify for power buttonFurquan Shaikh
None of the mainboards using Chrome EC set SCI mask for power button. Thus, the EC will never generate SCI for power button events. This change removes the Notify call for power button as part of clean up for getting rid of the power button device in coreboot. BUG=b:110913245 Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29chromeec platforms: Update ACPI throttle handler callMartin Roth
Currently the throttle event handler method THRT is defined as an extern, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24chromeec: Add support for controlling USB port powerEmil Lundmark
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be used to control the power state of up to 8 individual USB ports. Some Chromeboxes have their GPIO pins for controlling USB port power wired to the EC, so they cannot be accessed directly by coreboot. Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03ec/google/chromeec: Update Tablet event callMartin Roth
The tablet event handler method TPET is defined as an extern, then defined again in skylake, the only platform that supports it. In newer versions of IASL, this generates an error, as the method is defined in two places. Remove the extern and the CondRefOf check. That's not needed if we only set the EC_ENABLE_TABLET_EVENT define on platforms that have a TPET handler. Change-Id: I8bee069fc95637446593dfaaae1254e931421517 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12ec/chromeec: Fix battery ACPI mutex levelMatt DeVillier
Commit 07fe618 [chromeec: Add support for reading second battery info] added a mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-09chromeec: Fix ACPI compile warningLijian Zhao
For system without secondary battery, current DSDT will report warning during build time. Add a conditional check to make sure only battery index 0 can return success. TEST=Build pass. Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07chromeec: Add support for reading second battery infoNicolas Boichat
We share the same shared memory fields for both batteries. When the host wants to switch battery to read out, it will: - Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index - Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value - Then fetch the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23598 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-02ec/google/chromeec: Remove wake flag from keyboard IRQDuncan Laurie
The keyboard IRQ was changed to ExclusiveAndWake in order to support waking from suspend-to-idle (S0ix) with commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0 http://review.coreboot.org/11712 However this is triggering a kernel panic on Windows 10 because it apparently does not like legacy device interrupts to to be set as wake capable. This change is no longer necessary because the linux kernel was changed to always treat the keyboard as wake capable: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/input/serio/i8042.c?id=f13b2065de8147a1652b830ea5db961cf80c09df Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23563 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-26ec/google/chromeec: Add _PRW property to CREC deviceFurquan Shaikh
This change adds _PRW property to CREC device that allows Linux kernel to identify CREC as a wakeup source. BUG=b:69118395 TEST=Verified following steps: 1. Under sys devices for CREC: "echo enabled > wakeup" 2. Lid close/Lid open -- Verified that wakeup_count increases 3. Mode change -- Verified that wakeup_count increases Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-30chromeec: Notify CREC device of wakeup eventsFurquan Shaikh
Whenever there is a new EC event that could be wake-capable, notify CREC device of this using notification value 0x2 i.e. device wake. This allows Linux kernel to track active_count value correctly for CREC device. BUG=b:69118395 BRANCH=None TEST=Verified on Soraka: 1. Put device into suspend 2. Wake up using mode change/lid open 3. Check that the active_count for GOOG0004 has increased (cat wakeup_sources | grep GOOG0004) Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30ec/google: Use feature flag layout that matches the EC host commandPatrick Georgi
The EC side of the feature bits in ACPI EC space isn't stable yet, and we're now going for matching them up with the EC host command of the same purpose. Change-Id: I9c1f0e5390e840ea0c32315a3da8eea6f3e12f54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22ec/google: Detect keyboard backlight at runtimePatrick Georgi
This enables adding the backlight driver to boards that may or may not come with a keyboard backlight function. It's the responsibility of the EC to report if that feature exists, but that's not a big extra burden given that it already keeps track of everything else related to the backlight. BUG=b:64705535 BRANCH=none CQ-DEPEND=CL:620595 TEST=configured KBLE manually and noticed the presence/absence of /sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel, corresponding to the value reported by the EC. Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-28src/ec: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-02ec/google/chromeec: Fix typo in ECUI deviceDuncan Laurie
The IO region defined for EC_HOST_CMD_REGION1 was incorrectly using EC_HOST_CMD_REGION0 for the range maximum so the region was showing a minimum of 0x880 and a maximum of 0x800. Both min and max should report the same value as this region is fixed and cannot be relocated by the OS. Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22google/chromeec: Ensure \_SB.LID0 is present before using itFurquan Shaikh
Since we want to support devices that do not have a lid but still use EC, we need to conditionally check if referencing \_SB.LID0 is valid. BUG=b:35775024 Change-Id: I92433460ec870fb07f48e67a6dfc61e3c036a129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18941 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-09google/chromeec: Add support for cros_ec_keyb deviceFurquan Shaikh
This is required to pass button information from EC to kernel without using 8042 keyboard driver. 1. Define EC buttons device using GOOG0007 ACPI ID. 2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-07ec/google/chromeec: Add support for tablet mode switch driverGwendal Grignou
Add a new driver GOOG0006 to report tablet switch to user space. On glados based convertible, check that with a new kernel driver (cros_ec_tbmc) that evtest collects tablet switch changes. Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/430951 Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/18173 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15ec/chromeec: Correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString(). Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 05:57:20 +0000