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path: root/src/ec/google/chromeec/ec.c
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2020-11-18ec/google/chromeec: Add more wrappers for regulator controlYidi Lin
google_chromeec_regulator_enable is for enabling/disabling the regulator. google_chromeec_regulator_is_enabled is for querying if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20ec/google/chromeec: Add wrappers to get/set the voltageYidi Lin
Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-14src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)Divya Sasidharan
EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-14ec/google/chromeec: Add helper to request AP resetKarthikeyan Ramasubramanian
Add a helper function to initiate AP reset through Embedded Controller (EC). BUG=b:162290856 TEST=Ensure that the EC resets AP on boards where the command is supported. Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)Tim Wawrzynczak
A recent Coverity scan found an issue with the way the EC_HOST_EVENT_MASK macro was being used. It was being passed values between 0 and 63, but since it is doing basically (1ULL << (value - 1)), this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd bit of the mask. This is fixed by incrementing the start and end conditions of the loop by 1, so the event mask ranges from bits 0 to 63, instead of -1 to 62. Found-by: Coverity CID 1430218 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused 'include <bootmode.h>'Elyes HAOUAS
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTIONKyösti Mälkki
After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20google/chromeec: Add wrapper for EC_CMD_GET_KEYBD_CONFIGRajat Jain
Add a wrapper command for the subject command Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20google/chromeec: Revise parameters of EC USB PD API callGaggery Tsai
This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-16ec/google/chromeec: add BOARD_VERSION CBI supportAaron Durbin
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-09ec/google/chromeec: Replace uses of ec_current_image with ec_imageFurquan Shaikh
This change replaces all uses of ec_current_image with ec_image since Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum ec_current_image and instead changed it to enum ec_image. BUG=b:149987779 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-05src/ec: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06ec/google/chromeec: Fix dev ops for chromeecFurquan Shaikh
CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-18ec/google/chromeec: Add SSDT generator for ChromeOS ECTim Wawrzynczak
Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17vboot: push clear recovery mode switch until BS_WRITE_TABLESJoel Kitching
Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-01ec/google/chromeec: Add new wrappers for host commandsTim Wawrzynczak
Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-22ec/google/chromeec: add support for fw_config cbi fieldJett Rink
The firmware configuration (fw_config) field is store in the CBI EEPROM and it should be used to make firmware customization instead of sku/variant id. BUG=b:145519081 TEST=builds Change-Id: I790998a29e724ecdff8876cca072267537b7cea6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-29ec/google/chromeec: ignore LIMIT_POWER based on command code in responseRizwan Qureshi
Assume that LIMIT_POWER is not requested if the ec does not support it. Do this by checking the command code in the response message instead of return value. BUG=b:146165519 BRANCH=None TEST=Boot puff with EC which does not support LIMIT_POWER param. Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-27ec/google: Fix wedging AP on early ec sw syncTim Wawrzynczak
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power limits to reasonable defaults and can wedge the AP by browning out at the end of vboot. BRANCH=none BUG=b:146165519 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29ec/google/chromeec: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I09bca1897920871a6b29c25dc2bad94a8061da29 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37038 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04include: Remove EC_EVENT_* from elog.hYu-Ping Wu
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_* macros defined in ec_commands.h, which is synchronized from Chromium OS ec repository. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-31ec/google/chromeec: Add EC driver support for software syncTim Wawrzynczak
Quite a few new functions added here in order to support the use-case of performing EC software sync within coreboot. Most of these functions are related to retrieving the EC's hash, and writing a new image into the EC's flash. BUG=b:112198832 BRANCH=none TEST=With whole patch series, successfully performed EC software sync Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-29ec/google/chromeec: Clean up ec.[ch]Tim Wawrzynczak
Change all uN integral types to uintN_t. Make the names of host command params/responses consistent. Use static struct initialization to ensure all fields are initialized. BUG=none BRANCH=none TEST=compiles Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-09ec/google/chromeec: fix format security warningGreg V
Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35866 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23google/chromeos: Support AP watchdog flag from Chrome ECYou-Cheng Syu
After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag telling if the last reboot was triggered by AP watchdog for some boards (e.g., Kukui). This CL adds a new function google_chromeec_get_ap_watchdog_flag(), which reads the AP watchdog flag from Chrome EC, and updates the tables of reset causes and reset flags. A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for elog_handle_watchdog_tombstone() to determine if watchdog reset was triggered by the AP watchdog flag from EC instead of the tombstone in AP. BUG=b:109900671,b:118654976 BRANCH=none TEST=test with https://review.coreboot.org/c/coreboot/+/31843 Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-23ec/google/chromeec: Update ec_commands.hYou-Cheng Syu
Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574). Since ec_commands.h already defines usb_charge_mode and only USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is removed from ec.h. To avoid redefinition of the BIT macro, #ifndef check is added to include/types.h. BUG=b:109900671,b:118654976 BRANCH=none TEST=emerge-kukui -j coreboot Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21chromeec: Depend on events_copy_b to identify the wake sourceRavi Chandra Sadineni
google_chromec_get_event() depends on the main copy of EC which is used by ACPI subsytem in the kernel for querying events. google_chromeec_get_event() also clears the event from EC. Thus if the kernel has to identify the wake source, it has no way to do that. Thus instead depend on events_copy_b to log the wake source. Please look at go/hostevent-refactor for more info. BUG=b:133262012 BRANCH=None TEST=Hack hatch bios and make sure hostevent log is correct. Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20src/ec: Drop __PRE_RAM__ and __SMM__ guardsKyösti Mälkki
For files built in ramstage and smm -classes, testing for !__PRE_RAM__ is redundant. All chip_operations are exluded with use of DEVTREE_EARLY in static devicetree, so garbage collection will take care of the !__SMM__ cases. Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27ec/google/chromeec: fix the error status passingYH Lin
Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error -- fixing cbi_get_uint32() and cbi_get_string() so they follow the same convention. BUG=b:123676982 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Reviewed-on: https://review.coreboot.org/c/31585 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16ec/google/chromeec: add support for retrieving OEM nameWisley Chen
OEM name can be stored in CBI. This change can support for fetching the OEM name from CBI. BUG=b:118798180 TEST=Verified to get data from CBI Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-10-11ec/google/chromeec: Get rid of __SMM__ guard for chromeec functionsFurquan Shaikh
There doesn't seem to be a reason why we would want to protect certain chromeec functions with __SMM__ guard. So, this change gets rid of it. If the functions remain unused, then they would be removed during linking. Change-Id: I8196406074b01fe8ea15173c55d45bb86384be1b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-17ec/google/chromeec: check to see if s0ix is enabledPaul Moy
Make sure S0Ix is supported before trying to set up the EC's lazy wake mask. Change-Id: I78896ffe6312409c9f241b3b3224169c188bb265 Signed-off-by: Paul Moy <pmoy@chromium.org> Reviewed-on: https://review.coreboot.org/28610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08ec/google/chromeec: add support for retrieving DRAM part numberAaron Durbin
The DRAM part number can be stored in the CBI data. Therefore, add support for fetching the DRAM part number from CBI. BUG=b:112203105 TEST=Fetched data from CBI on phaser during testing. Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-27chromeec: Read EC uptime info on bootJonathan Brandmeyer
Additional diagnostic information about the EC and the most recent reasons why it has reset the AP are read out and logged via printk. This may aid in debugging spurious hangs and/or resets on the AP by providing traceability to the EC when it triggered the reset. Merely knowing that the EC was also recently reset may provide valuable intelligence. See also https://crrev.com/c/1139028. Change-Id: Ie6abe645d5acefb570b9f6a3c4a4b60d5bcd63cd Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27621 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27chromeec: Sync ec_commands.h with CrOS upstreamJonathan Brandmeyer
Update ec_commands.h to be a verbatim copy of upstream, except retain the complete copyright notice found in coreboot's copy. Upstream refers to a file not present in coreboot. Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-01ec/google/chromeec: Initialize SMI mask in google_chromeec_events_initFurquan Shaikh
This change adds smi_events to google_chromeec_event_info and allows mainboards to set SMI mask if current boot type is not S3 wakeup. Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08ec/google/chromeec: add config for wake event typesPatrick Georgi
Avoids array overflow Change-Id: Ia49a782ba6729c740e3b91c500120132983f6b3c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25992 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amodeDaisuke Nojiri
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port is connected to a device with alternate mode(s) and the call is made for the mode with the index higher than 0 (e.g. Zinger). Cros EC manages alternative modes entered in an array (amode[]). The command is designed to accept a query for an particular index and a particular SVID. Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries first time for DisplayPort with index=0, EC says 'no' as expected. AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00) is sent instead because cmd_code is cleared by google_chromeec_command. res.svid is supposed to be 0 when EC hits the last index + 1 but res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to the next index and this repeats forever. Any USB-C device with non-DisplayPort alternate mode can cause this hang unless HDMI port is used. This patch resets all the fields of chromeec_command in each iteration in case google_chromeec_command changes them. BUG=b:78630899 BRANCH=none TEST=Verify Fizz boots without monitors on Zinger. Verify the svid enumeration happens as expected. Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/25878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-01chromeec: fix an uninitialized local variableZhuohao Lee
google_chromeec_command() may only write the 1 or 2 bytes to variable r (4 bytes). However, this api returns 4 bytes data. To avaid returning the incorrect data, we need to initialize the local variable. BUG=b:76442548 BRANCH=none TEST=write 2 bytes data into the flash, then, read by cbi_get_uint32 Change-Id: I3395c97ab6bfd7882d7728310de8a29041190e76 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25460 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 14:43:47 +0000