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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.
This allows specifying an external path for the CrOS EC source path.
Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The mainboards which use the Chrome EC duplicate the
same logic in the mainboard smi handler. Provide common
helper functions for those boards to utilize.
BUG=chrome-os-partner:54977
Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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In particular, update host_event the original value for MKBP was not
set in ToT.
CQ-DEPEND=CL:353634
BUG=b:27849483
BRANCH=none
TEST=Compile on Samus. Tested in Cyan branch.
Change-Id: I0184e4f0e45c3321742d3138ae0178c159cbdd0a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: cc6750b705300f5b94bf23fe5485d6e7a5f9e327
Original-Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/354040
Reviewed-on: https://review.coreboot.org/15567
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to
implement rtc_get() so that this can be plumbed in.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits, boot on gru and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:44
Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:53
Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505
Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351780
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15302
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The Chrome OS bootloader is changing its EC software sync mechanism to
look for the hash of an EC image in a separate CBFS file, rather than
using the CBFS hash attribute of the image itself (see
http://crosreview.com/348061). This patch makes coreboot generate
appropriate hash files for the new format when it builds and bundles a
Chrome EC image. This also allows us to compress the EC image itself.
Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15039
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Allow EC to send an interrupt using ACPI SMI when a MKBP event
is available. This will be used by the sensor stack.
Update all ACPI branch except those without sensors with:
for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+
| cut -d '/' -f 2 | grep -v -e cyan -e lars); do
echo $i
cd $i
git diff ../lars/ec.h | patch -p 5
cd -
done
BUG=b:27849483
BRANCH=none
TEST=Compile on Samus. Tested in Cyan branch.
Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890
Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/342364
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14854
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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In order to allow using the same C source to be compiled
for multiple stages (with #if/#endif guards) one needs the
necessary function delcarations. Therefore, remove the
guards.
Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14796
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to provide other stages access to the ioport range
required by the ChromeEC provide google_chromeec_ioport_range()
function to fill in the details. Currently, the ioport range is
only consumed by the LPC implemenation. Also allow ec_lpc.c to be built
for the bootblock stage.
Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14769
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a GOOG0004 object that will be used to load cros_ec_lpc.
BUG=chromium:516122
BRANCH=none
TEST=Compile. Work in cyan branch.
Change-Id: Id8d9487ea6f376728eaa57728baceda7e5f6b2b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6380104986d2740a14fc74161fec9f2994d2affc
Original-Change-Id: I682d68e0858327ec7c0fbd0924dd9f99527d4df0
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/342363
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC;
however, those ports were not declared as a resource. This had two
major downsides:
* It allowed the allocator to assign said ports to other devices
* It required manually open up an IO window in the LPC bridge.
The LPC bridge on many chromeec boards had to be painstakingly
adjusted to meet these constraints.
The advantage of declaring the resources upfront is that the lpc
bridge can now scan its child resources and automatically open up
IO windows, as requested by its LPC children devices.
Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This file use stdint types, but does not include the appropriate
header. This creates a parasitic dependency on including stdint.h
before ec_commands.h. Fix that by including the necesarry header.
Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It's mobo architecture, not a user-adjustable setting.
Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13906
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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With the Chrome EC's "board" name set in Kconfig, the build system will
build and add the EC firmware, too. Available for the EC and the USB
PD controller.
Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13547
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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For x86 systems which resume through the reset vector one needs to
ensure the the RW slot taken at resume time matches the one at
boot time. To that end, allow Chrome OS EC to supply the plumbing
to vboot for storing and retrieving the RW slots' hash digest
using the vstore backend.
BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
which returns a bad hash to ensure that is properly caught.
Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75
Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323502
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13577
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add support functions for the Chrome EC temporary storage interface.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados with modified coreboot
Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88
Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315217
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update to the latest EC command header.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e
Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315216
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13571
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active. Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.
Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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TEST=Plug/Unplug AC Adapter multiple times and make sure device is
charging properly.
Original-Reviewed-on: https://chromium-review.googlesource.com/303990
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.
ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.
Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This patch removes the auto select of SERIRQ_CONTINUOUS_MODE
as part of the EC_GOOGLE_CHROMEEC_LPC.
BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.
Change-Id: I4aed2c53bfdcbb8f7cd28f9a23fad86c9cd5086e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 90a1e0785857a4da556e7664a8b83e9c8a0a78a7
Original-Change-Id: Ia411966bab557c269afa1d7e88ab2550eb35447e
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305580
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12155
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Recent version of iasl are flagging more things as warnings.
Remove unused Local0 uses and make _CRS method serialized to
fix these warnings.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build glados with iasl-20150717
Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e
Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302163
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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In order to wake from S0ix the kernel needs to know that the
keyboard interrupt is wake capable. Using IRQNoFlags does not
allow the wake capability to be reported.
For normal S3 this does not matter as the EC is the one handling
the keyboard wake event. For S0ix the EC does not need to be
involved in this particular wake event.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=echo freeze > /sys/power/state and wake from keyboard
Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373
Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/301441
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11712
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a kconfig entry to indicate that a board has a PD chip and
try to put it in RO mode before the EC during early init.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c
Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297747
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11571
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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coreboot has no CREDITS file.
Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Since more boards are starting to use the EC provided keyboard
backlight interface move the code to a common place and allow
it to get included in mainboards.
Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/11478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a helper function to read the EC switch state on LPC based
ECs instead of having each board need to understand and use the
specific EC LPC IO method that is required.
BUG=chrome-os-partner:43515
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293514
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11280
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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If the Host Command payload is less than 4 bytes
and is word aligned then the payload was not transferred at all.
EC reads the old packet and CRC mismatch occurs.
In this issue, the HC command packet
consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD
as payload encountered the same problem as above.
Hence select byte access mode for shorter payloads.
BRANCH=None
BUG=chrome-os-partner:42396
TEST=System should boot after
chromeos-firmwareupdate
Change-Id: I22bdb739108d31b592c20247be69c198d617d359
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f
Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286537
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11012
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9
Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280879
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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This change switches all ECs and the generic EC ACPI code
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in ec/Makefile.inc or in
ec/<vendor>/Makefile.inc.
This means, vendor and ec directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9798
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There's no need to have the VBOOT2_VERIFY_FIRMWARE
distinction because it's the only game in town.
Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9958
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Long auto-increment access cannot be used when our initial address is
misaligned or when our terminal address is misaligned on write
operations.
BUG=chrome-os-partner:38224
TEST=Verify host command functionality on cyan.
BRANCH=None
Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354
Original-Reviewed-on: https://chromium-review.googlesource.com/266653
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9987
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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MEC cannot access memmap-range data directly though LPC and instead must
access through its EMI unit.
BUG=chrome-os-partner:38224
TEST=Verify host command functionality on glower.
BRANCH=None
Change-Id: If98d425014a894ddeafad4268f92af5860878522
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c
Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/263611
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Rather than calling inb + outb directly, access the ports through common
functions. This is in preparation for alternative access modes required
by certain new embedded controllers.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Verify system boots cleanly in normal mode.
BRANCH=None
Change-Id: I98783ff67a37d970019683bb589825bc5d68c033
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030
Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/263571
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is set, access to memmap data
should go through the ACPI CMD / DATA ports.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify
system boots cleanly.
BRANCH=None
Change-Id: I9d19704df259f5a25e04a9b07b23968e93fe6302
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0b59b040a7889d2d1bd6eeaf57dd960bd29927d
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: I405e28828457a1fd83a7ece7192a7e7d0a37be95
Original-Reviewed-on: https://chromium-review.googlesource.com/262932
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9893
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Some platforms cannot access the 900h-9ffh region over the LPC bus, so
it's necessary to access memmap data over the ACPI cmd / data ports.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify
system boots cleanly and battery status is updated immediately on plug /
unplug.
BRANCH=None
Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d
Original-Reviewed-on: https://chromium-review.googlesource.com/262314
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/9886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:38224
TEST=Compile for Samus
BRANCH=None
Change-Id: I9bb7ed100b876cbd50d39f5c5ad599e4bd7be6b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca8fbf8ed91d95486f0c8db680e8ceabca597a3a
Original-Change-Id: I250fcce67f6103cf3037b416b8e74dd4a2cea780
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262313
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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src/ec/google/chromeec/ec_lpc.c: In function ‘google_chromeec_command_v3’:
src/ec/google/chromeec/ec_lpc.c:88:3: error: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘unsigned int’ [-Werror=format=]
printk(BIOS_ERR, "EC cannot send %ld bytes\n",
^
cc1: all warnings being treated as errors
Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Change-Id: I0d47350f00102a959d54a64b8f932099fc13f886
Reviewed-on: http://review.coreboot.org/9558
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Log the new EC panic host event.
BUG=chrome-os-partner:36985
TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in
previous boot" is seen in /var/log/eventlog.
BRANCH=Samus
Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7
Original-Reviewed-on: https://chromium-review.googlesource.com/252391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: http://review.coreboot.org/9508
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds a few retries to NVRAM read/write transactions with the
EC. Failing to read the NVRAM is not fatal to the boot, but it's still
pretty bad... especially since a single initial read failure will cause
vboot to blindly reinitialize the whole NVRAM with zeroes, destroying
important configuration bits like dev_boot_usb. The current EC
transaction timeout is one second, so the three retries added here can
potentially increase boot time by three seconds per transaction... but
this shouldn't happen in any normal case anyway, and if there are errors
a little extra wait is probably preferrable to nuking your NVRAM.
(Also, added a missing newline to an error message in the EC code.)
BRANCH=veyron
BUG=chrome-os-partner:36924
TEST=Booted a Jerry with the power button bug with a 2 second press,
noticed that the first two transactions failed but the third one
succeeded.
Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a
Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251694
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9507
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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With kconfig understanding wildcards, we don't need
Kconfig files that just include other Kconfig files
anymore.
Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9298
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Some ECs may require a few microseconds to ramp up their clock after
being awaken by /CS assertion. This adds a Kconfig variable that can
be overridden at the mainboard-level which will force a delay between
asserting /CS and beginning a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer
Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585
Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220242
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-on: http://review.coreboot.org/9217
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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The EC behavior for reading events from the ACPI interface was broken
with this commit:
d899fda lpc: ACPI query-next-event drops masked events
https://chromium-review.googlesource.com/194935
This is causing no EC wake events to be logged. To make sure they are
logged once again set the wake mask before querying for events.
Also remove the check for port80 event logging since this is no longer
used as we now store the port80 code in CMOS and this is unnecessary
commands to do for the resume path.
BUG=chrome-os-partner:32462
BRANCH=samus,auron
TEST=build and boot on samus, check for EC wake events for keyboard
and lid in the event log.
Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7
Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add a new host event to send a notify(0x80) to the battery
when the EC indicates that battery status has changed.
The kernel has fixed the bug with _BIX method so it can
be enabled now.
BUG=chrome-os-partner:32196
BRANCH=samus
TEST=build and boot on samus
Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2
Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220320
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9212
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to talk to the PD controller with a passthru command
coreboot needs to be able to use v3 commands.
The command version is automatically detected based on the
advertized flags from the EC.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot on samus EVT
Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e
Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Coreboot needs to be able to reboot the PD controller into RO
image in recovery mode early in the boot process in order to
avoid a lengthy recovery mode boot if it is only done at vboot
software sync time.
In order to do this a new device index field is added to the
command structure which must be initaalized to zero for all EC
transactions.
This early init and image check code is only used in romstage so
include it in the __PRE_RAM__ block.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=build and boot on samus EVT in recovery mode and see that
the PD is rebooted to RO mode early in the boot.
Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1
Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|