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2015-09-09chromeec: Add kconfig entry for EC PD supportDuncan Laurie
Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11571 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27chromeec: Add helper function to read EC switch stateDuncan Laurie
Add a helper function to read the EC switch state on LPC based ECs instead of having each board need to understand and use the specific EC LPC IO method that is required. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293514 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11280 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21mec: Correct the access mode for short payloadsJagadish Krishnamoorthy
If the Host Command payload is less than 4 bytes and is word aligned then the payload was not transferred at all. EC reads the old packet and CRC mismatch occurs. In this issue, the HC command packet consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD as payload encountered the same problem as above. Hence select byte access mode for shorter payloads. BRANCH=None BUG=chrome-os-partner:42396 TEST=System should boot after chromeos-firmwareupdate Change-Id: I22bdb739108d31b592c20247be69c198d617d359 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286537 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30EC: Add new EC host event for FASTBOOT_MODE requestFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9 Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280879 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-29kbuild: automatically include ECsStefan Reinauer
This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9798 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28chromeos: remove VBOOT2_VERIFY_FIRMWARE optionAaron Durbin
There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-27chromeec: ec_mec: Fix misaligned data accessShawn Nematbakhsh
Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9987 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Add variant MEC IOShawn Nematbakhsh
MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Read / write IO ports through common functionsShawn Nematbakhsh
Rather than calling inb + outb directly, access the ports through common functions. This is in preparation for alternative access modes required by certain new embedded controllers. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Verify system boots cleanly in normal mode. BRANCH=None Change-Id: I98783ff67a37d970019683bb589825bc5d68c033 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030 Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263571 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Access ID + flags through ACPI I/O portsShawn Nematbakhsh
If CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP is set, access to memmap data should go through the ACPI CMD / DATA ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly. BRANCH=None Change-Id: I9d19704df259f5a25e04a9b07b23968e93fe6302 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0b59b040a7889d2d1bd6eeaf57dd960bd29927d Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I405e28828457a1fd83a7ece7192a7e7d0a37be95 Original-Reviewed-on: https://chromium-review.googlesource.com/262932 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Support accessing memmap data over port 62/66Shawn Nematbakhsh
Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: Update ec_commands.h from EC repositoryShawn Nematbakhsh
BUG=chrome-os-partner:38224 TEST=Compile for Samus BRANCH=None Change-Id: I9bb7ed100b876cbd50d39f5c5ad599e4bd7be6b4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca8fbf8ed91d95486f0c8db680e8ceabca597a3a Original-Change-Id: I250fcce67f6103cf3037b416b8e74dd4a2cea780 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262313 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14chromeec: Fix printf formatting warningAnatol Pomozov
src/ec/google/chromeec/ec_lpc.c: In function ‘google_chromeec_command_v3’: src/ec/google/chromeec/ec_lpc.c:88:3: error: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘unsigned int’ [-Werror=format=] printk(BIOS_ERR, "EC cannot send %ld bytes\n", ^ cc1: all warnings being treated as errors Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com> Change-Id: I0d47350f00102a959d54a64b8f932099fc13f886 Reviewed-on: http://review.coreboot.org/9558 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
Log the new EC panic host event. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7 Original-Reviewed-on: https://chromium-review.googlesource.com/252391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: http://review.coreboot.org/9508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10cros_ec: Retry failed VBNV transactionsJulius Werner
This patch adds a few retries to NVRAM read/write transactions with the EC. Failing to read the NVRAM is not fatal to the boot, but it's still pretty bad... especially since a single initial read failure will cause vboot to blindly reinitialize the whole NVRAM with zeroes, destroying important configuration bits like dev_boot_usb. The current EC transaction timeout is one second, so the three retries added here can potentially increase boot time by three seconds per transaction... but this shouldn't happen in any normal case anyway, and if there are errors a little extra wait is probably preferrable to nuking your NVRAM. (Also, added a missing newline to an error message in the EC code.) BRANCH=veyron BUG=chrome-os-partner:36924 TEST=Booted a Jerry with the power button bug with a 2 second press, noticed that the first two transactions failed but the third one succeeded. Change-Id: I5d1cf29ac1c555ea2336ebb0b0e0a3f7cbb9c3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 894a8a0b4a9805e92544b5e3dfa90baf6d36649a Original-Change-Id: I6267cdda2be2bad34541b687404c2434d3be345b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251694 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02chromeec: Add wakeup delay after SPI /CS assertionDavid Hendricks
Some ECs may require a few microseconds to ramp up their clock after being awaken by /CS assertion. This adds a Kconfig variable that can be overridden at the mainboard-level which will force a delay between asserting /CS and beginning a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585 Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220242 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-on: http://review.coreboot.org/9217 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-02chromeec: Fix logging of EC wake eventsDuncan Laurie
The EC behavior for reading events from the ACPI interface was broken with this commit: d899fda lpc: ACPI query-next-event drops masked events https://chromium-review.googlesource.com/194935 This is causing no EC wake events to be logged. To make sure they are logged once again set the wake mask before querying for events. Also remove the check for port80 event logging since this is no longer used as we now store the port80 code in CMOS and this is unnecessary commands to do for the resume path. BUG=chrome-os-partner:32462 BRANCH=samus,auron TEST=build and boot on samus, check for EC wake events for keyboard and lid in the event log. Change-Id: Ib46fc00006ff0e5777941fc3ab1d81607359c4cb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b4dccc03bdded8411cc1429521579ea006ec58a7 Original-Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add battery status event and re-enable _BIXDuncan Laurie
Add a new host event to send a notify(0x80) to the battery when the EC indicates that battery status has changed. The kernel has fixed the bug with _BIX method so it can be enabled now. BUG=chrome-os-partner:32196 BRANCH=samus TEST=build and boot on samus Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2 Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220320 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add support for v3 commands on LPCDuncan Laurie
In order to talk to the PD controller with a passthru command coreboot needs to be able to use v3 commands. The command version is automatically detected based on the advertized flags from the EC. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot on samus EVT Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add commands to check PD image typeDuncan Laurie
Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Update ec_commands.h from EC repositoryDuncan Laurie
This latest version includes PD passthru support. BUG=chrome-os-partner:30079 BRANCH=None TEST=build and boot on samus Change-Id: Ie718b73a6b125a863ae28e63769dd54edc267f0b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fbca0743a4b45828a466d05afc3a2e94d2e3da2e Original-Change-Id: I79d160219564155008f6231fec35808d1fbd6f04 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218901 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-31chromeec: Clear post code before reboot to RODuncan Laurie
When doing an EC requested reboot to RO mode clear the saved post code in order to prevent confusing events in the log where the system is rebooted intentionally. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus, run FAFT, check for odd eventlog entries about last post code 0x31 when it is rebooted during samus romstage entry point. Original-Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e32d7a7e54e7006b84509dbc2bfe9b4b022eba71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iad816669fb4054260f995f6f0bfb140121aaddff Reviewed-on: http://review.coreboot.org/9176 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-27chromeec: Add ACPI device for PD MCU and handle related EC host eventShawn Nematbakhsh
Add ACPI device for PD MCU, if present. Call Notify routine when the corresponding EC host event is received. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host event, and verify ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214809 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit 226b349e40ed8eacce20d0a8063877382f707c69) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iecff6c06f1b37651ff61e36d6085d397d66f861c Reviewed-on: http://review.coreboot.org/8968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-21chromeec: use stopwatch APIAaron Durbin
Simplify the SPI timeout by using the stopwatch. BUG=None BRANCH=None TEST=Built nyan. Confirmed stopwatch works independently. Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1 Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219493 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: provide proto v3 over i2c supportAaron Durbin
Certain boards need to speak proto v3 over i2c. Leverage the transport agnostic API to share the logic with other proto v3 impelementations. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Can talk to the EC successfully. Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3 Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211139 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: allow transport implementation to provide buffers for proto v3Aaron Durbin
Depending on the transport mechanism for proto v3 different bytes need to be send and/or read before the request and response. Depending on the software and/or controller interface that requirement leads to needing to copy data into temporary buffers. Avoid this by allowing the transport mechanism to provide the request and response buffers. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built for rush and ryu. Ran on ryu with i2c implementation. Also built for rambi to check x86 systems. Change-Id: I35d4d69bd1fa900fc0cfe3822496f381405bdcb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7224426e1d0bcf06ed010131a2462a6ca201d8b Original-Change-Id: Iad6cce566a253ca72e6f5009a97235ece0a6c1b5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211138 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8827 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: correct response length for VBNV writeAaron Durbin
The EC doesn't return any data when one performs a write to VBNV context. Therefore there is a mismatch of expectations. Correct this by properly setting the expected response length. BUG=chrome-os-partner:31148 BRANCH=None TEST=No longer hanging while writing to VBNV on ryu. Change-Id: I7077a507c3280358dac1f88ece62cacee9b71bea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1735c3377163aeb9e90155cb9f081a1eea919c9 Original-Change-Id: I455724f20f5442bd62a792f09273227417475f07 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211137 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8826 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18chromeec: Move SERIQ mode to LPC optionMarc Jones
SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses. This fixes a KCONFIG unmet dependency warning on ARM mainboards with chromeec. Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8665 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27vboot2: read dev and recovery switchDaisuke Nojiri
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa Original-Reviewed-on: https://chromium-review.googlesource.com/206064 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1 Reviewed-on: http://review.coreboot.org/8162 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-09chrome ec: Add ACPI Device for ALS if enabledDuncan Laurie
The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f Reviewed-on: http://review.coreboot.org/8132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-30chromeos: Unconditionally clear the EC recovery requestSheng-Liang Song
Add the empty weak function clear_recovery_mode_switch(). Problem: If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set, the following will happen: 1. Boot device in recovery mode with Esc + F3 + Pwr. 2. Turn device off with Pwr button. 3. Turn device on with Pwr button. Device still boots to recovery screen with recovery_reason:0x02 recovery button pressed. If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the device off and on again with the Pwr button does a normal boot. Solution: Unconditionally clear the recovery flag. BUG=chromium:279607 BRANCH=TOT TEST=Compile OK. Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197780 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Commit-Queue: Sheng-liang Song <ssl@google.com> Original-Tested-by: Sheng-liang Song <ssl@google.com> (cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae Reviewed-on: http://review.coreboot.org/7895 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-16i2c: Replace the i2c API.Gabe Black
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins)
2014-09-29google/chromeec: Notify DPTF charger participant on AC state changeDuncan Laurie
The DPTF charger particpant device needs to be notified when the AC state changes so it can re-evaluate the PPCC object and apply the proper charge rate limit if necessary. Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189029 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brad Geltz <brad.geltz@intel.com> (cherry picked from commit ed1ee577014421b021e8814edc91a1b696bf9eed) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-19chrome ec: Add support for limiting charger currentDuncan Laurie
Update the ec_commands header (direct from EC source) and add support for the new charger current limit interface which will be used by DPTF. Change-Id: Ia9a2a84b612a2982dbe996f07a856be6cd53ebdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185758 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1fcca2d75856ecefd3aeb1c551182aa76d649466) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6925 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-13chromeos: On ARM platforms VBNV lives in the ECStefan Reinauer
This patch renames the x86 way of doing things to explicitly mention CMOS (which is not available on our ARM platforms) and adds an implementation to get VBNV through the Chrome EC. We might want to refine this further in the future to allow VBNV in the EC even on x86 platforms. Will be fixed when that appears. Also, not all ARM platforms running ChromeOS might use the Google EC in the future, in which case this code will need additional work. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901 Reviewed-on: https://chromium-review.googlesource.com/167540 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6616 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-08chromeec: Implement full battery workaround at 6%Duncan Laurie
Currently the workaround for indicating a "full" battery kicks in at 3%, but this turns out to be too high for some devices. So move the workaround start point to 6% from full, or 94%. Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6521 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-04chrome ec: Add Methods for new EC eventsDuncan Laurie
The EC recently added events for Thermal and Battery shutdown to provide some sort of notification to the OS that it is about to pull power. Original-Change-Id: Ibbdb5f11b8fa9fc80612a3cc10667c612420b1bb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> (cherry picked from commit 03a53ed5e58caa018d49df193510d95bdf5bed7b) Change-Id: I0cdf89a60b541840029db58d49921340e7ab60eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16d00848f48da83f6d6c813137a35af45bb05c4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25src/ec: Sanitize headers and comment #endif pairingsEdward O'Callaghan
Comment #endif /* FOO */ pairings. Alphabetise headers and remove any #if CONFIG_ guards around them. Background rational: Remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the same function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6059 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13chromeec: add function to reboot on unexpected imageAaron Durbin
It's helpful to have a generic function that will tell the EC to reboot if the EC isn't running a specified image. Add that and implement google_chromeec_early_init() to utilize the new function still maintaing its semantics of if recvoery mode is enabled the EC should be running its RO image. There is a slight change in that no communication is done with the EC if not in recovery mode. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Built and boot with recovery request. Noted EC reboot. Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182060 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5039 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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