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2018-09-14ec/lenovo/pmh7: support 9bit address spaceAlexander Couzens
The pmh7 has at least a 9bit address space. The h8s allows to access the 9th address space by using io port 0x15ed as second address register. The pmh7 is connected via SPI to the h8s. The h8s is acting as proxy to access the address space. Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-09-05mb/lenovo: Support dual graphics for xx20/xx30 ThinkPadsEvgeny Zinoviev
Add CMOS option that allows to use both integrated and discrete GPU. Tested on ThinkPad W530. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02chromeec: PS2K node can't be under SIO nodeStefan Reinauer
Some operating systems won't find the keyboard if it is under the SIO node. BRANCH=none BUG=none TEST=Boot Windows, observe that keyboard is working Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> Original-Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Original-Reviewed-on: https://chromium-review.googlesource.com/895364 Change-Id: If99e15bef2173c44cecaa8fdeaa69381bd0e499a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28eve: Specify a unique ID for PS2 devicesLucas Chen
Windows certification tests will fail if the PS2 devices are using Plug and Play ID (PNP0303). For all Chromebooks we should use GOOG000A. BRANCH=eve BUG=b:110066056 TEST=AltOS certification test verify. Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1098874 Reviewed-by: Matt Delco <delco@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23google/chromeec: Add support for "base attached switch" deviceDmitry Torokhov
On some detachables, the mere presence of attached base is not enough to determine whether the device is in tablet mode or not, so we introducing a new "switch" in EC, separate from "Tablet Mode" switch, to signal whether the base is attached or not. We also want the driver to be separate from cros_ec_keyb, so we create a new ACPI device, C(hrome)B(ase)A(ttached)S(witch), with HID GOOG000B, and guard it with EC_ENABLE_CBAS_DEVICE. Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28260 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20ec/lenovo/pmh7: use read/write function in clear_bit/set_bitAlexander Couzens
Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-17ec/google/chromeec: Fix ACPI FWTS errorMarc Jones
Fix the following FWTS error: FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line 3038 Line | AML source -------------------------------------------------------------------------------- 03035| Return (One) 03036| } 03037| 03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query | ^ | Warning 3115: Not all control paths return a value (_Q09) 03039| { 03040| If (Acquire (PATM, 0x03E8)) 03041| { ================================================================================ ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths do not return a value. All control paths that return must return a value otherwise unexpected behaviour may occur. This error occurs because a branch on an conditional op-code returns a value and another does not, which is inconsistent behaviour. _Q09 is a reserved method and can't return a value. Change the logic so that no return is used and avoid this test error. BUG=b:112476331 TEST=Run FWTS. Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-13ec/google/chromeec: de-dup a _UIDMatt Delco
There's two instances od _UID 1 for PNP0C02. This change moves the more system-specific instance of the two to a higher number. I believe these are the 4 I'm seeing. soc/intel/skylake/acpi/systemagent.asl Device (PDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) soc/intel/skylake/acpi/lpc.asl Device (LDRC) Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) ec/google/chromeec/acpi/superio.asl Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) ec/google/chromeec/acpi/superio.asl Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) Name (_UID, 3) Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09src/ec/google/chromeec: Fix typoElyes HAOUAS
Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08ec/google/chromeec: add support for retrieving DRAM part numberAaron Durbin
The DRAM part number can be stored in the CBI data. Therefore, add support for fetching the DRAM part number from CBI. BUG=b:112203105 TEST=Fetched data from CBI on phaser during testing. Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30ec/lenovo/h8/acpi: Fix ACPI error in _INIPatrick Rudolph
Store the power on defaults in the _REG method after the ERAM region is ready for use. It might not be ready when accessed from _INI. Tested on Lenovo T430. Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-27chromeec: Read EC uptime info on bootJonathan Brandmeyer
Additional diagnostic information about the EC and the most recent reasons why it has reset the AP are read out and logged via printk. This may aid in debugging spurious hangs and/or resets on the AP by providing traceability to the EC when it triggered the reset. Merely knowing that the EC was also recently reset may provide valuable intelligence. See also https://crrev.com/c/1139028. Change-Id: Ie6abe645d5acefb570b9f6a3c4a4b60d5bcd63cd Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27621 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27chromeec: Sync ec_commands.h with CrOS upstreamJonathan Brandmeyer
Update ec_commands.h to be a verbatim copy of upstream, except retain the complete copyright notice found in coreboot's copy. Upstream refers to a file not present in coreboot. Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://review.coreboot.org/27620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-26ec/roda: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: Ic35a232a9867936d3d84aa275ae50e3e3dd9bf97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27396 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26ec/quanta: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: I59eb60efeefcdbe8b2dc08e17453cf95bdfd39b1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27395 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26ec/compal: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: I10e2c6da0043eb291a8c6266b251054dbe599653 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27393 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26ec/google: pass ops to pnp_enable_devices instead of LDN-specific overrideFelix Held
Since ops was passed as override in the pnp_dev_info struct, the generic pnp_ops that was passed to pnp_enable_devices was never used. Change-Id: Id09c6cffb9a0cbbd9189c18801121449c9504422 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27394 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19ec/lenovo/h8/acpi: Apply state on wakePatrick Rudolph
Implement ACPI S3 resume control to restore the state before entering sleep. * Store the requested state wake state for bluetooth and WWAN. * Add new methods to init the state and apply the requested state on wake. * Call the new method on all devices. Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add UWB ACPI interfacePatrick Rudolph
Add ACPI methods GUWB and SUWB for thinkpad_acpi. Required for power control of the UWB module. Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/ssdt: Add keyboard backlight interfacePatrick Rudolph
Add methods MLCG and MLCS for thinkpad_acpi kernel module. Required for backlight or thinklight control from userspace. Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19ec/lenovo/h8/acpi: Add WWAN ACPI methodsPatrick Rudolph
Implement GWAN and SWAN for thinkpad_acpi kernel module. Both methods allow power control of the WWAN module. Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-09src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09ec/lenovo/h8/acpi: Add BDC interfacePatrick Rudolph
* Add SSDT generator to add dynamic ACPI code. * Implement GBDC and SBDC for thinkpad_acpi kernel module. Required for BDC power control from userspace. Tested on Lenovo T430: The bluetooth module is detected and can be powercycled using network manager. Change-Id: Ida825196650966194a883945896a038b0790fe45 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-06ec/lenovo/h8/acpi: Move ACPI HKEY device to new filePatrick Rudolph
Move the APCI HKEY device to a new file and include it. The follow-up commits will extend it and this way it remains readable. Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-03ec/google/chromeec: Remove keyboard initializationFurquan Shaikh
Since none of the boards using chromeec select DRIVERS_PS2_KEYBOARD now, there is no need to call pc_keyboard_init anymore. This change gets rid of the call and adds an error message in case any mainboard using chromeec tries to select this config. BUG=b:110024487 Change-Id: Ia0b56abe0a5990e527277eaf3397e00dccda3e50 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-02ec/google/chromeec: Remove notify for power buttonFurquan Shaikh
None of the mainboards using Chrome EC set SCI mask for power button. Thus, the EC will never generate SCI for power button events. This change removes the Notify call for power button as part of clean up for getting rid of the power button device in coreboot. BUG=b:110913245 Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-07google/chromeec: Set proper dev opsNaresh G Solanki
For enable_resource & set_resource, use default DEVICE_NOOP so that they are not reported as missing during enumeration. BUG=None BRANCH=None TEST= Build & boot soraka. Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04src/ec: Remove whitespace before tabElyes HAOUAS
Change-Id: Ib47cc1ee617aae74a8cfbcb25c1d0c083196f417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-01ec/google/chromeec: Initialize SMI mask in google_chromeec_events_initFurquan Shaikh
This change adds smi_events to google_chromeec_event_info and allows mainboards to set SMI mask if current boot type is not S3 wakeup. Change-Id: I899a6af6e57d295b4eac2039c8245ebcc73a42bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29chromeec platforms: Update ACPI throttle handler callMartin Roth
Currently the throttle event handler method THRT is defined as an extern, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24chromeec: Add support for controlling USB port powerEmil Lundmark
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be used to control the power state of up to 8 individual USB ports. Some Chromeboxes have their GPIO pins for controlling USB port power wired to the EC, so they cannot be accessed directly by coreboot. Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08ec/google/chromeec: add config for wake event typesPatrick Georgi
Avoids array overflow Change-Id: Ia49a782ba6729c740e3b91c500120132983f6b3c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25992 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08ec/lenovo/h8: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I3db9487c46b29510e59ec5c019d022f5cbaff354 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-03ec/google/chromeec: Update Tablet event callMartin Roth
The tablet event handler method TPET is defined as an extern, then defined again in skylake, the only platform that supports it. In newer versions of IASL, this generates an error, as the method is defined in two places. Remove the extern and the CondRefOf check. That's not needed if we only set the EC_ENABLE_TABLET_EVENT define on platforms that have a TPET handler. Change-Id: I8bee069fc95637446593dfaaae1254e931421517 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30cros-ec: Avoid infinitely looping in google_chromeec_pd_get_amodeDaisuke Nojiri
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port is connected to a device with alternate mode(s) and the call is made for the mode with the index higher than 0 (e.g. Zinger). Cros EC manages alternative modes entered in an array (amode[]). The command is designed to accept a query for an particular index and a particular SVID. Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries first time for DisplayPort with index=0, EC says 'no' as expected. AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00) is sent instead because cmd_code is cleared by google_chromeec_command. res.svid is supposed to be 0 when EC hits the last index + 1 but res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to the next index and this repeats forever. Any USB-C device with non-DisplayPort alternate mode can cause this hang unless HDMI port is used. This patch resets all the fields of chromeec_command in each iteration in case google_chromeec_command changes them. BUG=b:78630899 BRANCH=none TEST=Verify Fizz boots without monitors on Zinger. Verify the svid enumeration happens as expected. Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/25878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-01chromeec: fix an uninitialized local variableZhuohao Lee
google_chromeec_command() may only write the 1 or 2 bytes to variable r (4 bytes). However, this api returns 4 bytes data. To avaid returning the incorrect data, we need to initialize the local variable. BUG=b:76442548 BRANCH=none TEST=write 2 bytes data into the flash, then, read by cbi_get_uint32 Change-Id: I3395c97ab6bfd7882d7728310de8a29041190e76 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25460 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-26ec/purism: Fix CPU Turbo value (PPCM) set by the ECYouness Alaoui
The EC needs to set the PPCM value depending on whether Turbo is enabled or not, and the values differ between Broadwell (0, 1) and Skylake (1, 2) platforms. Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-09ec/google/chromeec: Add boardid.c to bootblockMartin Roth
Update build so that we can get the board ID in bootblock. BUG=b:74248569 TEST=build and boot grunt with follow-on patch. Bayhub part is disabled. Change-Id: I6353bcb4abcef4e8dc2b625082e33b73525c8525 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-07ec/google/chromeec: Fix typo preventing PD EC firmware inclusionBen Pye
Change-Id: I12ae0d556c43d3d6537cac5d8f640e6a960101ae Signed-off-by: Ben Pye <ben@curlybracket.co.uk> Reviewed-on: https://review.coreboot.org/25017 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-05ec/chromeec: Fix check for UHEPI supportMatt DeVillier
Commit 1dfc2c3 [google/chromeec: Enable unified host event programming interface] added support for UHEPI, but google_chromeec_is_uhepi_supported() incorrectly treats negative error return codes from google_chromeec_check_feature() as supported. Fix this check to only treat positive return values as supported, as per the original intent. Test: boot google/lulu, verify cbmem console reports UHEPI not supported even if feature check returns error code, verify lid/kb wake events correctly wakes the device from S3/sleep. Change-Id: I7846efb340bc1546b074e8502daf906c444bd146 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02ec/google/chromeec: Add note before error messageMartin Roth
When clearing events from the EC, an error is returned when we try to clear an event that doesn't exist. This is normal, but can be distracting when trying to track down an error, so add a message saying that the error is expected. BUG=None Test=Build Grunt with SMM debug enabled. See message before "EC returned error result code 1". Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/24914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26ec/google/chromeec: Remove extra newline characters from printkFurquan Shaikh
This change removes extra newline characters from print statements for wake masks. Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-17chromeec: Sync ec_commands.h for CBI tagsDaisuke Nojiri
This patch syncs ec_commands.h with the one in chromeec. BUG=b:70294260 BRANCH=none TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz. Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17chromeec: Add google_chromeec_wait_for_displayDaisuke Nojiri
The google_chromeec_wait_for_display API checks whether a display is ready or not. It waits in a loop until EC says it entered DisplayPort alternative mode or times out in 2 seconds. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-17chromeec: Add google_chromeec_pd_get_amodeDaisuke Nojiri
The google_chromeec_pd_get_amode API checks whether TCPM is in a specified alternate mode or not. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 09:29:25 +0000