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2016-10-07ec/google/chromeec: Add minimum delay between SPI CS assertionsJulius Werner
Some Chrome OS ECs require a small amount of time after a SPI transaction to reset their controllers before they can service the next CS assertion. The kernel and depthcharge have always enforced a 200us minimum delay for this... coreboot should've done the same. BRANCH=gru BUG=chrome-os-partner:58046 TEST=Booted Kevin in recovery mode, confirmed that recovery events got logged with correct timestamps in eventlog. Change-Id: I32ec343f3293ac93729d3e6e2f43d7605a396cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9e4696533d4318ae7c8715b71ab963d8897c16c Original-Change-Id: I6a7baf7859d5d50e299495d118e7890dcaa2c1b0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/392206 Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/16885 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-26mainboards,ec: provide common declaration for mainboard_ec_init()Aaron Durbin
Add a header file to provide common declarations that the mainboards can use regarding EC init. BUG=chrome-os-partner:56677 Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16734 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-09-26ec/google/chromeec: provide optional ASL lid switch implementationAaron Durbin
Instead of relying on the mainboards to provide their own LID0 ACPI device, provide the infrastructure so that the mainboards can signal to the EC ASL code to provide the default lid switch implementation. BUG=chrome-os-partner:56677 Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16732 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-07src/ec: Improve code formattingElyes HAOUAS
Change-Id: I93b71ca577c973046d1651d92665168b329eda1b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16503 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Omar Pakker
2016-08-31src/ec: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I013f71b702644ab337c3d76be1489530bad6e6cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16322 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-20google/chromeec: Ensure data is ready before reading itFurquan Shaikh
Before reading the data provided by EC to the host, ensure that data ready flag is set. Otherwise, it could result in reading stale/incorrect data from the data buffer. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is read correctly by host on reef. Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16258 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-12chromeec/acpi: add Tablet event and EC ACPI MEMjiazi Yang
Switch DPTF table when TABLET/NOTEBOOK mode changes 1. EC send EC_HOST_EVENT_MODE_CHANGE(29/0x1D) when mode changes 2. Host read current "physical mode" from EC ERAM BUG=chrome-os-partner:53526 BRANCH=master TEST=build glados Change-Id: I836d2b9d1a24c455c4b8d4b85f7edc19259d2f71 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9506c4c07e0f713c9a22a0231bc4255f6876783f Original-Change-Id: I5a3363ff9c958decb5aed1c85fc2a1ef6670931d Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/365991 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08google/chromeec: Enable/Disable ccache with config variableMartin Roth
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as blank on the Chrome EC make command line. This will overrride and disable the CCACHE variable in the Chrome EC makefile. Change-Id: Idb1da06941084cea104d77748820971edf151f7b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16035 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31build system: really disable building CrEC when not neededPatrick Georgi
Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively ignore anything related to EC firmware board names if enabled. BUG=none BRANCH=none CQ-DEPEND=CL:344540 TEST=emerge-samus coreboot works Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233 Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345584 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Original-Commit-Queue: Martin Roth <martinroth@chromium.org> Original-Trybot-Ready: Martin Roth <martinroth@chromium.org> Original-Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15938 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-27chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding pathPaul Kocialkowski
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS EC source path, with a fallback to 3rdparty/chromeec. This allows specifying an external path for the CrOS EC source path. Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-15ec/google/chromeec: provide common SMI handler helpersAaron Durbin
The mainboards which use the Chrome EC duplicate the same logic in the mainboard smi handler. Provide common helper functions for those boards to utilize. BUG=chrome-os-partner:54977 Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15685 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-10google/chromeec: Update EC command headerGwendal Grignou
In particular, update host_event the original value for MKBP was not set in ToT. CQ-DEPEND=CL:353634 BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I0184e4f0e45c3321742d3138ae0178c159cbdd0a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: cc6750b705300f5b94bf23fe5485d6e7a5f9e327 Original-Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354040 Reviewed-on: https://review.coreboot.org/15567 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24ec/google: Add support for the EC 'get time' functionSimon Glass
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to implement rtc_get() so that this can be plumbed in. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits, boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505 Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351780 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-03chromeec: Move EC image hash to separate file in CBFSJulius Werner
The Chrome OS bootloader is changing its EC software sync mechanism to look for the hash of an EC image in a separate CBFS file, rather than using the CBFS hash attribute of the image itself (see http://crosreview.com/348061). This patch makes coreboot generate appropriate hash files for the new format when it builds and bundles a Chrome EC image. This also allows us to compress the EC image itself. Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15039 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-13ec/google/chromeec: don't guard function declarationsAaron Durbin
In order to allow using the same C source to be compiled for multiple stages (with #if/#endif guards) one needs the necessary function delcarations. Therefore, remove the guards. Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14796 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-11ec/google/chromeec: provide way to query ioport rangeAaron Durbin
In order to provide other stages access to the ioport range required by the ChromeEC provide google_chromeec_ioport_range() function to fill in the details. Currently, the ioport range is only consumed by the LPC implemenation. Also allow ec_lpc.c to be built for the bootblock stage. Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14769 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-09ec/google/chromeec/acpi: Add GOOG0004 to load cros_ec_lpc dynamically.Gwendal Grignou
Add a GOOG0004 object that will be used to load cros_ec_lpc. BUG=chromium:516122 BRANCH=none TEST=Compile. Work in cyan branch. Change-Id: Id8d9487ea6f376728eaa57728baceda7e5f6b2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6380104986d2740a14fc74161fec9f2994d2affc Original-Change-Id: I682d68e0858327ec7c0fbd0924dd9f99527d4df0 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06ec/google/chromeec/ec_lpc: Declare used IO ports as a resourceAlexandru Gagniuc
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14585 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-06ec/google/chromeec/ec_commands.h: Include stdint.hAlexandru Gagniuc
This file use stdint types, but does not include the appropriate header. This creates a parasitic dependency on including stdint.h before ec_commands.h. Fix that by including the necesarry header. Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-10ec/lenovo/h8: do not reset volume on s3 wakeupChristopher Spinrath
On s3 wakeup h8_enable is called which resets the (audio) volume. But the volume should be the same as before the s3 state. In particular, userland programs (e.g. pulseaudio) may be out of sync, if the volume can be changed by hardware buttons also emitting acpi events. Hence, do not reset the volume on s3 wakeup. Tested on a Lenovo ThinkPad X220. Change-Id: I2af08dea1a3f14a40734d67d372e845cc18c5e09 Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-on: https://review.coreboot.org/14183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-03-05Hide EC_GOOGLE_CHROMEEC_SPI_BUS.Vladimir Serbinenko
It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13906 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ASL: Remove unused modulo recipient.Vladimir Serbinenko
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13619 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09Workaround for unused variable warning.Vladimir Serbinenko
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13624 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09stout: Fix ASL warningsVladimir Serbinenko
Change-Id: I1ddf37aa61fe95ad632c35d8041aed02fb1e8c01 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13533 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09build system: Build Chrome EC firmware on requestPatrick Georgi
With the Chrome EC's "board" name set in Kconfig, the build system will build and add the EC firmware, too. Available for the EC and the USB PD controller. Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13547 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04google/chromeec: implement vboot_(save|retrieve)_hash APIAaron Durbin
For x86 systems which resume through the reset vector one needs to ensure the the RW slot taken at resume time matches the one at boot time. To that end, allow Chrome OS EC to supply the plumbing to vboot for storing and retrieving the RW slots' hash digest using the vstore backend. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75 Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323502 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13577 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Add temporary storage interfaceDuncan Laurie
Add support functions for the Chrome EC temporary storage interface. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados with modified coreboot Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88 Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315217 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Update EC command headerDuncan Laurie
Update to the latest EC command header. BUG=chrome-os-partner:46049 BRANCH=none TEST=emerge-glados coreboot Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315216 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-31h8/battery: Fix ASL warning.Vladimir Serbinenko
Change-Id: Idf74e400efa3fea8eb74f372e4f261ab6567db8a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13513 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-28ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.Freddy Paul
TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12748 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21ec: Add support for EC used on Purism Librem laptopsDuncan Laurie
This adds basic ACPI support for the EC used on Purism Librem laptops. The EC firmware appears to use the topstar laptop interface that has support in the linux kernel for handling the special keys. Supported functions: - Battery information - AC presence - Lid switch - Special keys (after loading topstar-laptop driver in linux) - EC events for turbo enable/disable when on AC power Things it does not do: - EC SMI handling - Fan is left under EC control This was developed and tested on a Librem 13 laptop, and has not been directly tested on an Librem 15. Change-Id: Ib85a24e4cc8ab09b14147060043cff372863c2d1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/13025 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14ec/: add missing license headersMartin Roth
thermal.asl was written as part of the coreboot project, so gets the standard coreboot license header. ec_commands.h came from the chrome ec tree, so gets the BSD license from that tree as mentioned in the header that has been replaced. Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-26ACPI: Add hack to avoid IASL warning when reading back registersMartin Roth
Upcoming versions of IASL give a warning about unused methods. This adds an operation after the read to use the local variable and avoid the warning. The warning can be completely disabled on the command line, but as it can find real issues, my preference is to not do that. Fixes warnings: dsdt.aml 640: Store (CTMP, Local0) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24ec/quanta/ene_kb3940q: Fix ACPI NoticeMartin Roth
Affects these mainboards: - lenovo/g505s - google/parrot - hp/pavilion_m6_1035dx Fixes IASL notice for this specific instance: dsdt.aml 1952: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: Id297cdea35d43f51887f798a9983629343c2313a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24ec/lenovo/h8: Fix IASL warningsMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably the MKHP method wouldn't get called unless there were a pending event, but if no event is found, return a zero. Fixes IASL warning: dsdt.aml 1785: Method (MHKP, 0, NotSerialized) Warning 3115 - ^ Not all control paths return a value (MHKP) This was the only IASL warning in most lenovo mainboards. Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27ec/chrome: Disable LPC Continuous Serial IRQ Selectpchandri
This patch removes the auto select of SERIRQ_CONTINUOUS_MODE as part of the EC_GOOGLE_CHROMEEC_LPC. BUG=chrome-os-partner:44993 BRANCH=none TEST=Builds and Boots on fab3 kunimitsu. Change-Id: I4aed2c53bfdcbb8f7cd28f9a23fad86c9cd5086e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90a1e0785857a4da556e7664a8b83e9c8a0a78a7 Original-Change-Id: Ia411966bab557c269afa1d7e88ab2550eb35447e Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/305580 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-15ec/google: Move label to BOL to satisfy lint-testsPatrick Georgi
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11886 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-28chromeec: Fix ACPI compile warningsDuncan Laurie
Recent version of iasl are flagging more things as warnings. Remove unused Local0 uses and make _CRS method serialized to fix these warnings. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302163 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28ec: superio: Report keyboard IRQ as wake capableDuncan Laurie
In order to wake from S0ix the kernel needs to know that the keyboard interrupt is wake capable. Using IRQNoFlags does not allow the wake capability to be reported. For normal S3 this does not matter as the EC is the one handling the keyboard wake event. For S0ix the EC does not need to be involved in this particular wake event. BUG=chrome-os-partner:43079 BRANCH=none TEST=echo freeze > /sys/power/state and wake from keyboard Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373 Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/301441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-09chromeec: Add kconfig entry for EC PD supportDuncan Laurie
Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11571 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 10:38:35 +0000